return ret;
}
mem8_t __fastcall iopHwRead8_generic( u32 addr ) { return _generic_read<mem8_t>( addr ); }
mem16_t __fastcall iopHwRead16_generic( u32 addr ) { return _generic_read<mem16_t>( addr ); }
mem32_t __fastcall iopHwRead32_generic( u32 addr ) { return _generic_read<mem32_t>( addr ); }
//////////////////////////////////////////////////////////////////////////////////////////
//
void __fastcall iopHwWrite8_Page1( u32 addr, mem8_t val )
{
// all addresses are assumed to be prefixed with 0x1f801xxx:
pxAssert( (addr >> 12) == 0x1f801 );
u32 masked_addr = pgmsk( addr );
switch( masked_addr )
{
mcase(HW_SIO_DATA): sioWrite8( val ); break;
// for use of serial port ignore for now
//case 0x50: serial_write8( val ); break;
mcase(HW_DEV9_DATA): DEV9write8( addr, val ); break;
mcase(HW_CDR_DATA0): cdrWrite0( val ); break;
mcase(HW_CDR_DATA1): cdrWrite1( val ); break;
mcase(HW_CDR_DATA2): cdrWrite2( val ); break;
mcase(HW_CDR_DATA3): cdrWrite3( val ); break;
static __forceinline T _HwRead_16or32_Page1( u32 addr )
{
HwAddrPrep( 1 );
// all addresses should be aligned to the data operand size:
jASSUME(
( sizeof(T) == 2 && (addr & 1) == 0 ) ||
( sizeof(T) == 4 && (addr & 3) == 0 )
);
u32 masked_addr = pgmsk( addr );
T ret;
// ------------------------------------------------------------------------
// Counters, 16-bit varieties!
//
// Note: word reads/writes to the uppoer halfword of the 16 bit registers should
// just map to the HW memory map (tested on real IOP) -- ie, a write to the upper
// halfword of 0xcccc will have those upper values return 0xcccc always.
//
if( masked_addr >= 0x100 && masked_addr < 0x130 )
{
int cntidx = ( masked_addr >> 4 ) & 0xf;
switch( masked_addr & 0xf )
{
case 0x0:
ret = (T)IopCounters::ReadCount16( cntidx );
break;
case 0x4:
ret = IopCounters::ReadMode( cntidx );
break;
case 0x8:
ret = (T)IopCounters::ReadTarget16( cntidx );
break;
default:
ret = psxHu32(addr);
break;
}
}
