int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
{
if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
else
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC);
} else {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC);
}
if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
hwmgr->od_enabled = true;
return 0;
}
void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}
void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
#if defined(CONFIG_ACPI)
if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
#endif
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPatchPowerState);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPowerManagement);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SMC);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_FanSpeedInTableIsRPM);
return;
}
int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EVV);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
if (hwmgr->chip_id != CHIP_POLARIS10)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SPLLShutdownSupport);
if (hwmgr->chip_id != CHIP_POLARIS11) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
}
return 0;
}
/**
* Private Function used during initialization.
* @param hwmgr Pointer to the hardware manager.
* @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE).
* @param cap Which capability to set/reset.
*/
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
{
if (setIt)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
else
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
}
int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MemorySpreadSpectrumSupport);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EngineSpreadSpectrumSupport);
return 0;
}
int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EVV);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
return 0;
}
static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
int result = 0;
struct rv_hwmgr *data;
data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
result = rv_initialize_dpm_defaults(hwmgr);
if (result != 0) {
pr_err("rv_initialize_dpm_defaults failed\n");
return result;
}
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerPlaySupport);
rv_populate_clock_table(hwmgr);
result = rv_get_system_info_data(hwmgr);
if (result != 0) {
pr_err("rv_get_system_info_data failed\n");
return result;
}
rv_construct_boot_state(hwmgr);
result = phm_construct_table(hwmgr, &rv_setup_asic_master,
&(hwmgr->setup_asic));
if (result != 0) {
pr_err("Fail to construct setup ASIC\n");
return result;
}
result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
&(hwmgr->power_down_asic));
if (result != 0) {
pr_err("Fail to construct power down ASIC\n");
return result;
}
result = phm_construct_table(hwmgr, &rv_set_power_state_master,
&(hwmgr->set_power_state));
if (result != 0) {
pr_err("Fail to construct set_power_state\n");
return result;
}
result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
&(hwmgr->disable_dynamic_state_management));
if (result != 0) {
pr_err("Fail to disable_dynamic_state\n");
return result;
}
result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
&(hwmgr->enable_dynamic_state_management));
if (result != 0) {
pr_err("Fail to enable_dynamic_state\n");
return result;
}
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
RAVEN_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels =
RAVEN_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.vbiosInterruptId = 0;
hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
rv_init_vq_budget_table(hwmgr);
return result;
}
static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
struct cgs_system_info sys_info = {0};
int result;
rv_hwmgr->ddi_power_gating_disabled = 0;
rv_hwmgr->bapm_enabled = 1;
rv_hwmgr->dce_slow_sclk_threshold = 30000;
rv_hwmgr->disable_driver_thermal_policy = 1;
rv_hwmgr->thermal_auto_throttling_treshold = 0;
rv_hwmgr->is_nb_dpm_enabled = 1;
rv_hwmgr->dpm_flags = 1;
rv_hwmgr->disable_smu_acp_s3_handshake = 1;
rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
rv_hwmgr->gfx_off_controled_by_driver = false;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicM3Arbiter);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ACP);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_GFXDynamicMGPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableVoltageIsland);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (!result) {
if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_GFXDynamicMGPowerGating);
}
return 0;
}
static int init_thermal_controller(
struct pp_hwmgr *hwmgr,
const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
{
const ATOM_Vega10_Thermal_Controller *thermal_controller;
const Vega10_PPTable_Generic_SubTable_Header *header;
const ATOM_Vega10_Fan_Table *fan_table_v1;
const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
thermal_controller = (ATOM_Vega10_Thermal_Controller *)
(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table->usThermalControllerOffset));
PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
"Thermal controller table not set!", return -EINVAL);
hwmgr->thermal_controller.ucType = thermal_controller->ucType;
hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
hwmgr->thermal_controller.fanInfo.bNoFan =
(0 != (thermal_controller->ucFanParameters &
ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
thermal_controller->ucFanParameters &
ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
hwmgr->thermal_controller.fanInfo.ulMinRPM =
thermal_controller->ucFanMinRPM * 100UL;
hwmgr->thermal_controller.fanInfo.ulMaxRPM =
thermal_controller->ucFanMaxRPM * 100UL;
hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
= 100000;
set_hw_cap(
hwmgr,
ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
PHM_PlatformCaps_ThermalController);
if (!powerplay_table->usFanTableOffset)
return 0;
header = (const Vega10_PPTable_Generic_SubTable_Header *)
(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table->usFanTableOffset));
if (header->ucRevId == 10) {
fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
"Invalid Input Fan Table!", return -EINVAL);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
le16_to_cpu(fan_table_v1->usFanRPMMax);
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
le16_to_cpu(fan_table_v1->usThrottlingRPM);
hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
le16_to_cpu(fan_table_v1->usFanAcousticLimit);
hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
le16_to_cpu(fan_table_v1->usTargetTemperature);
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
le16_to_cpu(fan_table_v1->usTargetGfxClk);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
le16_to_cpu(fan_table_v1->usFanGainEdge);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
le16_to_cpu(fan_table_v1->usFanGainHotspot);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
le16_to_cpu(fan_table_v1->usFanGainLiquid);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
le16_to_cpu(fan_table_v1->usFanGainVrVddc);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
le16_to_cpu(fan_table_v1->usFanGainPlx);
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
le16_to_cpu(fan_table_v1->usFanGainHbm);
hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
fan_table_v1->ucEnableZeroRPM;
hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
le16_to_cpu(fan_table_v1->usFanStopTemperature);
hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
le16_to_cpu(fan_table_v1->usFanStartTemperature);
} else if (header->ucRevId > 10) {
