static int pil_mss_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = dev_get_drvdata(pil->dev); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_Q6_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_MODEM_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_NC_HALT_BASE); /* * If the shutdown function is called before the reset function, clocks * and power will not be enabled yet. Enable them here so that register * writes performed during the shutdown succeed. */ if (drv->is_booted == false) { pil_mss_power_up(pil->dev); pil_q6v5_enable_clks(pil); } pil_q6v5_shutdown(pil); pil_q6v5_disable_clks(pil); pil_mss_power_down(pil->dev); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }
static int pil_mss_reset(struct pil_desc *pil) { struct q6v5_data *drv = dev_get_drvdata(pil->dev); int ret; writel_relaxed(0, drv->restart_reg); mb(); /* * Bring subsystem out of reset and enable required * regulators and clocks. */ ret = pil_mss_power_up(pil->dev); if (ret) goto err_power; ret = pil_q6v5_enable_clks(pil); if (ret) goto err_clks; /* Program Image Address */ if (drv->self_auth) writel_relaxed(drv->start_addr, drv->rmb_base + RMB_MBA_IMAGE); else writel_relaxed((drv->start_addr >> 4) & 0x0FFFFFF0, drv->reg_base + QDSP6SS_RST_EVB); ret = pil_q6v5_reset(pil); if (ret) goto err_q6v5_reset; /* Wait for MBA to start. Check for PBL and MBA errors while waiting. */ if (drv->self_auth) { ret = wait_for_mba_ready(pil->dev); if (ret) goto err_auth; } drv->is_booted = true; return 0; err_auth: pil_q6v5_shutdown(pil); err_q6v5_reset: pil_q6v5_disable_clks(pil); err_clks: pil_mss_power_down(pil->dev); err_power: return ret; }
static int pil_lpass_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base); if (drv->is_booted == false) pil_lpass_enable_clks(drv); pil_q6v5_shutdown(pil); pil_lpass_disable_clks(drv); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }
static int pil_lpass_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base); /* * If the shutdown function is called before the reset function, clocks * will not be enabled yet. Enable them here so that register writes * performed during the shutdown succeed. */ if (drv->is_booted == false) pil_lpass_enable_clks(drv); pil_q6v5_shutdown(pil); pil_lpass_disable_clks(drv); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }