void bl1_plat_set_ep_info(unsigned int image_id,
entry_point_info_t *ep_info)
{
unsigned int data = 0;
uintptr_t tmp = HIKEY960_NS_TMP_OFFSET;
if (image_id != NS_BL1U_IMAGE_ID)
panic();
/* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */
memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET,
NS_BL1U_SIZE);
memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE);
inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
/* Initialize the GIC driver, cpu and distributor interfaces */
gicv2_driver_init(&hikey960_gic_data);
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
/* CNTFRQ is read-only in EL1 */
write_cntfrq_el0(plat_get_syscnt_freq2());
data = read_cpacr_el1();
do {
data |= 3 << 20;
write_cpacr_el1(data);
data = read_cpacr_el1();
} while ((data & (3 << 20)) != (3 << 20));
INFO("cpacr_el1:0x%x\n", data);
ep_info->args.arg0 = 0xffff & read_mpidr();
ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
* This duplicates what the primary cpu did after a cold boot in BL1. The same
* needs to be done when a cpu is hotplugged in. This function could also over-
* ride any EL3 setup done by BL1 as this code resides in rw memory.
******************************************************************************/
void psci_arch_setup(void)
{
#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
/* Program the counter frequency */
write_cntfrq_el0(plat_get_syscnt_freq2());
#endif
/* Initialize the cpu_ops pointer. */
init_cpu_ops();
/* Having initialized cpu_ops, we can now print errata status */
print_errata_status();
}
void generic_delay_timer_init(void)
{
/* Value in ticks */
unsigned int mult = MHZ_TICKS_PER_SEC;
/* Value in ticks per second (Hz) */
unsigned int div = plat_get_syscnt_freq2();
/* Reduce multiplier and divider by dividing them repeatedly by 10 */
while ((mult % 10 == 0) && (div % 10 == 0)) {
mult /= 10;
div /= 10;
}
generic_delay_timer_init_args(mult, div);
}
