/*************************************************************************
* @b EVM_init()
*
* @n
*
* Initializes the platform hardware. This routine is configured to start in
* the evm.cfg configuration file. It is the first routine that BIOS
* calls and is executed before Main is called. If you are debugging within
* CCS the default option in your target configuration file may be to execute
* all code up until Main as the image loads. To debug this you should disable
* that option.
*
* @param[in] None
*
* @retval
* None
************************************************************************/
void EVM_init()
{
platform_init_flags sFlags;
platform_init_config sConfig;
/* Status of the call to initialize the platform */
int32_t pform_status;
/* Platform Information - we will read it form the Platform Library */
platform_info sPlatformInfo;
int core;
/*
* You can choose what to initialize on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0; /* PLLs for clocking */
sFlags.ddr = 0; /* External memory */
sFlags.tcsl = 1; /* Time stamp counter */
sFlags.phy = 1; /* Ethernet */ //ToDo: Shouldn't this better be 0 ?
sFlags.ecc = 0; /* Memory ECC */
sConfig.pllm = 0; /* Use libraries default clock divisor */
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialized the platform okay */
if (pform_status == Platform_EOK) {
/* Get information about the platform so we can use it in various places */
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
platform_get_info(&sPlatformInfo);
number_of_cores = sPlatformInfo.cpu.core_count;
MultiProc_setLocalId((Uint16) platform_get_coreid());
} else {
/* Initialization of the platform failed... die */
logout("Platform failed to initialize. Error code %d \n", pform_status);
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
}
}
/* Unlock the chip registers */
CSL_BootCfgUnlockKicker();
/* wake up the other core to run slave part */
for (core = 1; core < CORE_AMOUNT; core++)
{
/* IPC interrupt other cores */
DEVICE_REG32_W(IPCGR(core), 1);
platform_delay(1000);
}
}
static void cortexa_reset(target *t)
{
/* This mess is Xilinx Zynq specific
* See Zynq-7000 TRM, Xilinx doc UG585
*/
#define ZYNQ_SLCR_UNLOCK 0xf8000008
#define ZYNQ_SLCR_UNLOCK_KEY 0xdf0d
#define ZYNQ_SLCR_PSS_RST_CTRL 0xf8000200
target_mem_write32(t, ZYNQ_SLCR_UNLOCK, ZYNQ_SLCR_UNLOCK_KEY);
target_mem_write32(t, ZYNQ_SLCR_PSS_RST_CTRL, 1);
/* Try hard reset too */
platform_srst_set_val(true);
platform_srst_set_val(false);
/* Spin until Xilinx reconnects us */
platform_timeout timeout;
platform_timeout_set(&timeout, 1000);
volatile struct exception e;
do {
TRY_CATCH (e, EXCEPTION_ALL) {
apb_read(t, DBGDIDR);
}
} while (!platform_timeout_is_expired(&timeout) && e.type == EXCEPTION_ERROR);
if (e.type == EXCEPTION_ERROR)
raise_exception(e.type, e.msg);
platform_delay(100);
cortexa_attach(t);
}
bool cortexa_attach(target *t)
{
struct cortexa_priv *priv = t->priv;
int tries;
/* Clear any pending fault condition */
target_check_error(t);
/* Enable halting debug mode */
uint32_t dbgdscr = apb_read(t, DBGDSCR);
dbgdscr |= DBGDSCR_HDBGEN | DBGDSCR_ITREN;
dbgdscr = (dbgdscr & ~DBGDSCR_EXTDCCMODE_MASK) | DBGDSCR_EXTDCCMODE_STALL;
apb_write(t, DBGDSCR, dbgdscr);
DEBUG("DBGDSCR = 0x%08"PRIx32"\n", dbgdscr);
target_halt_request(t);
tries = 10;
while(!platform_srst_get_val() && !target_halt_poll(t, NULL) && --tries)
platform_delay(200);
if(!tries)
return false;
/* Clear any stale breakpoints */
for(unsigned i = 0; i < priv->hw_breakpoint_max; i++) {
apb_write(t, DBGBCR(i), 0);
}
priv->hw_breakpoint_mask = 0;
priv->bcr0 = 0;
platform_srst_set_val(false);
return true;
}
int hpdspuaStart (void) {
uint32_t coreId;
QMSS_CFG_T qmss_cfg;
CPPI_CFG_T cppi_cfg;
/* determine the core number. */
coreId = CSL_chipReadReg (CSL_CHIP_DNUM);
led_no=coreId;
platform_write("num of cores %d starts twinkling its LED\n", number_of_cores);
platform_write("core = %d starts twinkling its LED\n", coreId);
//platform_uart_init();
//platform_uart_set_baudrate(115200);
// write_uart("AAAAAAAA");
gpioInit();
gpioSetDirection(GPIO_10 ,GPIO_IN); //DOUTA pin
gpioSetDirection(GPIO_3 ,GPIO_OUT); //CNVST pin
gpioSetDirection(GPIO_13 ,GPIO_OUT); //CS pin
gpioSetDirection(GPIO_7 ,GPIO_OUT); //SCLK
//ADDR = 0, VA1 and VB1 are sampled; ADDR =1, VA2 and VB2 are sampled
//Right now VA1 and VB1 are being sampled
gpioSetOutput(GPIO_7); //By default clock high
gpioSetOutput(GPIO_3); // by default conversion pin high
gpioSetOutput(GPIO_13); // BY Default CS pin high
gpioSetFallingEdgeInterrupt(GPIO_10);
gpioSetRisingEdgeInterrupt(GPIO_10);
gpioEnableGlobalInterrupt();
//Wait for 100us before starting first conversion
platform_delay(100);
int rc=0;
while(1) {
if(coreId==0)
{
if (platform_get_coreid() == 0)
{
qmss_cfg.master_core = 1;
}
else
{
qmss_cfg.master_core = 0;
}
qmss_cfg.max_num_desc = MAX_NUM_DESC;
qmss_cfg.desc_size = MAX_DESC_SIZE;
qmss_cfg.mem_region = Qmss_MemRegion_MEMORY_REGION0;
if (res_mgr_init_qmss (&qmss_cfg) != 0)
{
platform_write ("Failed to initialize the QMSS subsystem \n");
goto main_exit;
}
else
{
platform_write ("QMSS successfully initialized \n");
}
if (platform_get_coreid() == 0)
{
cppi_cfg.master_core = 1;
}
else
{
cppi_cfg.master_core = 0;
}
cppi_cfg.dma_num = Cppi_CpDma_PASS_CPDMA;
cppi_cfg.num_tx_queues = NUM_PA_TX_QUEUES;
cppi_cfg.num_rx_channels = NUM_PA_RX_CHANNELS;
if (res_mgr_init_cppi (&cppi_cfg) != 0)
{
platform_write ("Failed to initialize CPPI subsystem \n");
goto main_exit;
}
else
{
platform_write ("CPPI successfully initialized \n");
}
if (res_mgr_init_pass()!= 0) {
platform_write ("Failed to initialize the Packet Accelerator \n");
goto main_exit;
}
else
{
platform_write ("PA successfully initialized \n");
}
rc = NC_SystemOpen( NC_PRIORITY_HIGH, NC_OPMODE_INTERRUPT );
if( rc ) {
platform_write("NC_SystemOpen Failed (%d). Will die in an infinite loop so you need to reset...\n",rc);
for(;;);
}
platform_write("HUA version %s\n", BLM_VERSION);
hCfg = CfgNew();
if( !hCfg )
{
platform_write("Unable to create a configuration for the IP stack.\n");
goto main_exit;
}
strcpy (HostName, "tidemo-");
i = strlen(HostName);
j = strlen(gPlatformInfo.serial_nbr);
if (j > 0) {
if (j > 6) {
memcpy (&HostName[i], &gPlatformInfo.serial_nbr[j-6], 6);
HostName[i+7] = '\0';
}
else {
memcpy (&HostName[i], gPlatformInfo.serial_nbr, j);
HostName[i+j+1] = '\0';
}
}
if( strlen( DomainName ) >= CFG_DOMAIN_MAX ||
strlen( HostName ) >= CFG_HOSTNAME_MAX )
{
platform_write("Domain or Host Name too long\n");
goto main_exit;
}
platform_write("Setting hostname to %s \n", HostName);
platform_write("MAC Address: %02X-%02X-%02X-%02X-%02X-%02X \n",
gPlatformInfo.emac.efuse_mac_address[0], gPlatformInfo.emac.efuse_mac_address[1],
gPlatformInfo.emac.efuse_mac_address[2], gPlatformInfo.emac.efuse_mac_address[3],
gPlatformInfo.emac.efuse_mac_address[4], gPlatformInfo.emac.efuse_mac_address[5]);
CfgAddEntry( hCfg, CFGTAG_SYSINFO, CFGITEM_DHCP_HOSTNAME, 0,
strlen(HostName), (uint8_t *)HostName, 0 );
if (!platform_get_switch_state(1)) {
CI_IPNET NA;
CI_ROUTE RT;
IPN IPTmp;
bzero( &NA, sizeof(NA) );
NA.IPAddr = inet_addr(EVMStaticIP);
NA.IPMask = inet_addr(LocalIPMask);
strcpy( NA.Domain, DomainName );
CfgAddEntry( hCfg, CFGTAG_IPNET, 1, 1, sizeof(CI_IPNET), (uint8_t *)&NA, 0 );
bzero( &RT, sizeof(RT) );
RT.IPDestAddr = inet_addr(PCStaticIP);
RT.IPDestMask = inet_addr(LocalIPMask);
RT.IPGateAddr = inet_addr(GatewayIP);
CfgAddEntry( hCfg, CFGTAG_ROUTE, 0, 1, sizeof(CI_ROUTE), (uint8_t *)&RT, 0 );
platform_write("EVM in StaticIP mode at %s\n",EVMStaticIP);
platform_write("Set IP address of PC to %s\n", PCStaticIP);
}
rc = DBG_WARN;
CfgAddEntry( hCfg, CFGTAG_OS, CFGITEM_OS_DBGPRINTLEVEL,
CFG_ADDMODE_UNIQUE, sizeof(uint), (uint8_t *)&rc, 0 );
rc = 64000;
CfgAddEntry( hCfg, CFGTAG_IP, CFGITEM_IP_SOCKTCPTXBUF,
CFG_ADDMODE_UNIQUE, sizeof(uint), (uint8_t *)&rc, 0 );
rc = 64000;
CfgAddEntry( hCfg, CFGTAG_IP, CFGITEM_IP_SOCKTCPRXBUF,
CFG_ADDMODE_UNIQUE, sizeof(uint), (uint8_t *)&rc, 0 );
rc = 64000;
CfgAddEntry( hCfg, CFGTAG_IP, CFGITEM_IP_SOCKTCPRXLIMIT,
CFG_ADDMODE_UNIQUE, sizeof(uint), (uint8_t *)&rc, 0 );
rc = 8192;
CfgAddEntry( hCfg, CFGTAG_IP, CFGITEM_IP_SOCKUDPRXLIMIT,
CFG_ADDMODE_UNIQUE, sizeof(uint), (uint8_t *)&rc, 0 );
do
{
rc = NC_NetStart( hCfg, NetworkOpen, NetworkClose, NetworkIPAddr );
} while( rc > 0 );
platform_write("Done with this utility. Shutting things down\n");
CfgFree( hCfg );
main_exit:
platform_write("Exiting the system\n");
//NC_SystemClose();
TaskExit();
return(0);
}
else
{
while(1)
{
platform_write("done processing .exiting core %d \n", coreId);
platform_delay(300000);
break;
}
platform_delay(300000);
break;
}
}
platform_write("done processing .exiting core %d", coreId);
platform_delay(3000000);
return 0;
}
void EVM_init()
{
platform_init_flags sFlags;
platform_init_config sConfig;
int32_t pform_status;
platform_info sPlatformInfo;
/* Initialise the UART
* You can choose what to initialise on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0; /* PLLs for clocking */
sFlags.ddr = 1; /* External memory */
sFlags.tcsl = 1; /* Time stamp counter */
sFlags.phy = 1; /* Ethernet */
sFlags.ecc = 0; /* Memory ECC */
sConfig.pllm = 0; /* Use libraries default clock divisor */
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialised the platform okay */
if (pform_status != Platform_EOK) {
/* Initialisation of the platform failed... die */
platform_write("Platform failed to initialise. Error code %d \n", pform_status);
platform_write("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
}
}
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
memset( (void *) &gPlatformInfo, 0, sizeof(platform_info));
platform_get_info(&sPlatformInfo);
//platform_get_info(&sPlatformInfo);
platform_get_info(&gPlatformInfo);
number_of_cores = gPlatformInfo.cpu.core_count;
//MultiProc_setLocalId((Uint16) platform_get_coreid());
platform_uart_init();
platform_uart_set_baudrate(115200);
platform_write_configure (PLATFORM_WRITE_ALL);
platform_write("Board Name %s \n",sPlatformInfo.board_name);
//write_uart("\r\n\r\nBooting Hello World image from NAND flash via IBL over I2C 0x51 ...");
//MultiProc_setLocalId((Uint16) platform_get_coreid());
//CSL_init();
//Uint16 eventId0;
//IRQ_clear(eventId0);
//eventId0 = TIMER_getEventId(timer0Handle);
//IRQ_enable(eventId0);
//IRQ_globalEnable();
return;
}
