/* Used to give a 32k clock to EMW1062 wifi rf module */
OSStatus host_platform_init_wlan_powersave_clock( void )
{
#if defined ( MICO_USE_WIFI_32K_CLOCK_MCO ) && defined ( MICO_USE_WIFI_32K_PIN )
platform_gpio_set_alternate_function( wifi_control_pins[WIFI_PIN_32K_CLK].port, wifi_control_pins[WIFI_PIN_32K_CLK].pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_MCO );
/* enable LSE output on MCO1 */
RCC_MCO1Config( RCC_MCO1Source_LSE, RCC_MCO1Div_1 );
return kNoErr;
#elif defined ( MICO_USE_WIFI_32K_PIN )
return host_platform_deinit_wlan_powersave_clock( );
#else
return kNoErr;
#endif
}
OSStatus platform_pwm_init( const platform_pwm_t* pwm, uint32_t frequency, float duty_cycle )
{
TIM_TimeBaseInitTypeDef tim_time_base_structure;
TIM_OCInitTypeDef tim_oc_init_structure;
RCC_ClocksTypeDef rcc_clock_frequencies;
uint16_t period = 0;
float adjusted_duty_cycle = ( ( duty_cycle > 100.0f ) ? 100.0f : duty_cycle );
OSStatus err = kNoErr;
require_action_quiet( pwm != NULL, exit, err = kParamErr);
platform_mcu_powersave_disable();
RCC_GetClocksFreq( &rcc_clock_frequencies );
if ( pwm->tim == TIM1 || pwm->tim == TIM8 || pwm->tim == TIM9 || pwm->tim == TIM10 || pwm->tim == TIM11 )
{
RCC_APB2PeriphClockCmd( pwm->tim_peripheral_clock, ENABLE );
period = (uint16_t)( rcc_clock_frequencies.PCLK2_Frequency / frequency - 1 ); /* Auto-reload value counts from 0; hence the minus 1 */
}
else
{
RCC_APB1PeriphClockCmd( pwm->tim_peripheral_clock, ENABLE );
period = (uint16_t)( rcc_clock_frequencies.PCLK1_Frequency / frequency - 1 ); /* Auto-reload value counts from 0; hence the minus 1 */
}
/* Set alternate function */
platform_gpio_set_alternate_function( pwm->pin->port, pwm->pin->pin_number, GPIO_OType_PP, GPIO_PuPd_UP, pwm->gpio_af );
/* Time base configuration */
tim_time_base_structure.TIM_Period = (uint32_t) period;
tim_time_base_structure.TIM_Prescaler = (uint16_t) 1; /* Divide clock by 1+1 to enable a count of high cycle + low cycle = 1 PWM cycle */
tim_time_base_structure.TIM_ClockDivision = 0;
tim_time_base_structure.TIM_CounterMode = TIM_CounterMode_Up;
tim_time_base_structure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit( pwm->tim, &tim_time_base_structure );
/* PWM1 Mode configuration */
tim_oc_init_structure.TIM_OCMode = TIM_OCMode_PWM1;
tim_oc_init_structure.TIM_OutputState = TIM_OutputState_Enable;
tim_oc_init_structure.TIM_OutputNState = TIM_OutputNState_Enable;
tim_oc_init_structure.TIM_Pulse = (uint16_t) ( adjusted_duty_cycle * (float) period / 100.0f );
tim_oc_init_structure.TIM_OCPolarity = TIM_OCPolarity_High;
tim_oc_init_structure.TIM_OCNPolarity = TIM_OCNPolarity_High;
tim_oc_init_structure.TIM_OCIdleState = TIM_OCIdleState_Reset;
tim_oc_init_structure.TIM_OCNIdleState = TIM_OCIdleState_Set;
switch ( pwm->channel )
{
case 1:
{
TIM_OC1Init( pwm->tim, &tim_oc_init_structure );
TIM_OC1PreloadConfig( pwm->tim, TIM_OCPreload_Enable );
break;
}
case 2:
{
TIM_OC2Init( pwm->tim, &tim_oc_init_structure );
TIM_OC2PreloadConfig( pwm->tim, TIM_OCPreload_Enable );
break;
}
case 3:
{
TIM_OC3Init( pwm->tim, &tim_oc_init_structure );
TIM_OC3PreloadConfig( pwm->tim, TIM_OCPreload_Enable );
break;
}
case 4:
{
TIM_OC4Init( pwm->tim, &tim_oc_init_structure );
TIM_OC4PreloadConfig( pwm->tim, TIM_OCPreload_Enable );
break;
}
default:
{
break;
}
}
exit:
platform_mcu_powersave_enable();
return err;
}
OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
{
DMA_InitTypeDef dma_init_structure;
USART_InitTypeDef uart_init_structure;
uint32_t uart_number;
OSStatus err = kNoErr;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
require_action_quiet( (optional_ring_buffer == NULL) || ((optional_ring_buffer->buffer != NULL ) && (optional_ring_buffer->size != 0)), exit, err = kParamErr);
uart_number = platform_uart_get_port_number( peripheral->port );
driver->rx_size = 0;
driver->tx_size = 0;
driver->last_transmit_result = kNoErr;
driver->last_receive_result = kNoErr;
driver->peripheral = (platform_uart_t*)peripheral;
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore( &driver->tx_complete, 1 );
mico_rtos_init_semaphore( &driver->rx_complete, 1 );
mico_rtos_init_semaphore( &driver->sem_wakeup, 1 );
mico_rtos_init_mutex ( &driver->tx_mutex );
#else
driver->tx_complete = false;
driver->rx_complete = false;
#endif
/* Configure TX and RX pin_mapping */
platform_gpio_set_alternate_function( peripheral->pin_tx->port, peripheral->pin_tx->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
platform_gpio_set_alternate_function( peripheral->pin_rx->port, peripheral->pin_rx->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
if ( ( peripheral->pin_cts != NULL ) && ( config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS ) )
{
platform_gpio_set_alternate_function( peripheral->pin_cts->port, peripheral->pin_cts->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
}
if ( ( peripheral->pin_rts != NULL ) && ( config->flow_control == FLOW_CONTROL_RTS || config->flow_control == FLOW_CONTROL_CTS_RTS ) )
{
platform_gpio_set_alternate_function( peripheral->pin_rts->port, peripheral->pin_rts->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
}
#ifndef NO_MICO_RTOS
if(config->flags & UART_WAKEUP_ENABLE) {
mico_rtos_init_semaphore( driver->sem_wakeup, 1 );
mico_rtos_create_thread(NULL, MICO_APPLICATION_PRIORITY, "UART_WAKEUP", thread_wakeup, 0x100, driver);
}
#endif
/* Enable UART peripheral clock */
uart_peripheral_clock_functions[ uart_number ]( uart_peripheral_clocks[ uart_number ], ENABLE );
uart_init_structure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
uart_init_structure.USART_BaudRate = config->baud_rate;
uart_init_structure.USART_WordLength = ( ( config->data_width == DATA_WIDTH_9BIT ) || ( ( config->data_width == DATA_WIDTH_8BIT ) && ( config->parity != NO_PARITY ) ) ) ? USART_WordLength_9b : USART_WordLength_8b;
uart_init_structure.USART_StopBits = ( config->stop_bits == STOP_BITS_1 ) ? USART_StopBits_1 : USART_StopBits_2;
switch ( config->parity )
{
case NO_PARITY:
uart_init_structure.USART_Parity = USART_Parity_No;
break;
case EVEN_PARITY:
uart_init_structure.USART_Parity = USART_Parity_Even;
break;
case ODD_PARITY:
uart_init_structure.USART_Parity = USART_Parity_Odd;
break;
default:
err = kParamErr;
goto exit;
}
switch ( config->flow_control )
{
case FLOW_CONTROL_DISABLED:
uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
break;
case FLOW_CONTROL_CTS:
uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_CTS;
break;
case FLOW_CONTROL_RTS:
uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS;
break;
case FLOW_CONTROL_CTS_RTS:
uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
break;
default:
err = kParamErr;
goto exit;
}
/* Initialise USART peripheral */
USART_DeInit( peripheral->port );
USART_Init( peripheral->port, &uart_init_structure );
/**************************************************************************
* Initialise STM32 DMA registers
* Note: If DMA is used, USART interrupt isn't enabled.
**************************************************************************/
/* Enable DMA peripheral clock */
if ( peripheral->tx_dma_config.controller == DMA1 )
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
}
else
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
}
/* Fill init structure with common DMA settings */
dma_init_structure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dma_init_structure.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init_structure.DMA_Priority = DMA_Priority_VeryHigh;
dma_init_structure.DMA_FIFOMode = DMA_FIFOMode_Disable;
dma_init_structure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
dma_init_structure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
dma_init_structure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
if ( config->data_width == DATA_WIDTH_9BIT )
{
dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
}
else
{
dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
}
/* Initialise TX DMA */
DMA_DeInit( peripheral->tx_dma_config.stream );
dma_init_structure.DMA_Channel = peripheral->tx_dma_config.channel;
dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &peripheral->port->DR;
dma_init_structure.DMA_Memory0BaseAddr = (uint32_t) 0;
dma_init_structure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
dma_init_structure.DMA_BufferSize = 0xFFFF; // This parameter will be configured during communication
dma_init_structure.DMA_Mode = DMA_Mode_Normal;
DMA_Init( peripheral->tx_dma_config.stream, &dma_init_structure );
/* Initialise RX DMA */
DMA_DeInit( peripheral->rx_dma_config.stream );
dma_init_structure.DMA_Channel = peripheral->rx_dma_config.channel;
dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &peripheral->port->DR;
dma_init_structure.DMA_Memory0BaseAddr = (uint32_t) 0;
dma_init_structure.DMA_DIR = DMA_DIR_PeripheralToMemory;
dma_init_structure.DMA_BufferSize = 0xFFFF; // This parameter will be configured during communication
dma_init_structure.DMA_Mode = DMA_Mode_Normal;
DMA_Init( peripheral->rx_dma_config.stream, &dma_init_structure );
/**************************************************************************
* Initialise STM32 DMA interrupts
**************************************************************************/
/* Configure TX DMA interrupt on Cortex-M3 */
NVIC_EnableIRQ( peripheral->tx_dma_config.irq_vector );
/* Enable TC (transfer complete) and TE (transfer error) interrupts on source */
clear_dma_interrupts( peripheral->tx_dma_config.stream, peripheral->tx_dma_config.complete_flags | peripheral->tx_dma_config.error_flags );
DMA_ITConfig( peripheral->tx_dma_config.stream, DMA_INTERRUPT_FLAGS, ENABLE );
/* Enable USART interrupt vector in Cortex-M3 */
NVIC_EnableIRQ( uart_irq_vectors[uart_number] );
USART_DMACmd( driver->peripheral->port, USART_DMAReq_Tx, DISABLE );
/* Enable USART */
USART_Cmd( peripheral->port, ENABLE );
/* Enable both transmit and receive */
peripheral->port->CR1 |= USART_CR1_TE;
peripheral->port->CR1 |= USART_CR1_RE;
/* Setup ring buffer */
if ( optional_ring_buffer != NULL )
{
/* Note that the ring_buffer should've been initialised first */
driver->rx_buffer = optional_ring_buffer;
driver->rx_size = 0;
receive_bytes( driver, optional_ring_buffer->buffer, optional_ring_buffer->size, 0 );
}
else
{
/* Not using ring buffer. Configure RX DMA interrupt on Cortex-M3 */
NVIC_EnableIRQ( peripheral->rx_dma_config.irq_vector );
/* Enable TC (transfer complete) and TE (transfer error) interrupts on source */
clear_dma_interrupts( peripheral->rx_dma_config.stream, peripheral->rx_dma_config.complete_flags | peripheral->rx_dma_config.error_flags );
DMA_ITConfig( peripheral->rx_dma_config.stream, DMA_INTERRUPT_FLAGS, ENABLE );
}
exit:
MicoMcuPowerSaveConfig(true);
return err;
}
platform_result_t platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
{
SPI_InitTypeDef spi_init;
platform_result_t result;
uint8_t spi_number;
wiced_assert( "bad argument", ( spi != NULL ) && ( config != NULL ) );
platform_mcu_powersave_disable();
spi_number = platform_spi_get_port_number( spi->port );
/* Init SPI GPIOs */
platform_gpio_set_alternate_function( spi->pin_clock->port, spi->pin_clock->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, spi->gpio_af );
platform_gpio_set_alternate_function( spi->pin_mosi->port, spi->pin_mosi->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, spi->gpio_af );
platform_gpio_set_alternate_function( spi->pin_miso->port, spi->pin_miso->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, spi->gpio_af );
/* Init the chip select GPIO */
platform_gpio_init( config->chip_select, OUTPUT_PUSH_PULL );
platform_gpio_output_high( config->chip_select );
/* Calculate prescaler */
result = calculate_prescaler( config->speed, &spi_init.SPI_BaudRatePrescaler );
if ( result != PLATFORM_SUCCESS )
{
platform_mcu_powersave_enable();
return result;
}
/* Configure data-width */
if ( config->bits == 8 )
{
spi_init.SPI_DataSize = SPI_DataSize_8b;
}
else if ( config->bits == 16 )
{
if ( config->mode & SPI_USE_DMA )
{
platform_mcu_powersave_enable();
/* 16 bit mode is not supported for a DMA */
return PLATFORM_UNSUPPORTED;
}
spi_init.SPI_DataSize = SPI_DataSize_16b;
}
else
{
platform_mcu_powersave_enable();
/* Requested mode is not supported */
return PLATFORM_UNSUPPORTED;
}
/* Configure MSB or LSB */
if ( config->mode & SPI_MSB_FIRST )
{
spi_init.SPI_FirstBit = SPI_FirstBit_MSB;
}
else
{
spi_init.SPI_FirstBit = SPI_FirstBit_LSB;
}
/* Configure mode CPHA and CPOL */
if ( config->mode & SPI_CLOCK_IDLE_HIGH )
{
spi_init.SPI_CPOL = SPI_CPOL_High;
}
else
{
spi_init.SPI_CPOL = SPI_CPOL_Low;
}
if ( config->mode & SPI_CLOCK_RISING_EDGE )
{
spi_init.SPI_CPHA = ( config->mode & SPI_CLOCK_IDLE_HIGH ) ? SPI_CPHA_2Edge : SPI_CPHA_1Edge;
}
else
{
spi_init.SPI_CPHA = ( config->mode & SPI_CLOCK_IDLE_HIGH ) ? SPI_CPHA_1Edge : SPI_CPHA_2Edge;
}
/* Enable SPI peripheral clock */
spi_peripheral_clock_functions[ spi_number ]( spi_peripheral_clocks[ spi_number ], ENABLE );
spi_init.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
spi_init.SPI_Mode = SPI_Mode_Master;
spi_init.SPI_NSS = SPI_NSS_Soft;
spi_init.SPI_CRCPolynomial = 0x7; /* reset value */
SPI_CalculateCRC( spi->port, DISABLE );
/* Init and enable SPI */
SPI_Init( spi->port, &spi_init );
SPI_Cmd ( spi->port, ENABLE );
platform_mcu_powersave_enable();
return WICED_SUCCESS;
}
OSStatus host_platform_bus_init( void )
{
SPI_InitTypeDef spi_init;
DMA_InitTypeDef dma_init_structure;
uint32_t a;
platform_mcu_powersave_disable();
mico_rtos_init_semaphore(&spi_transfer_finished_semaphore, 1);
/* Enable SPI_SLAVE DMA clock */
if ( wifi_spi.tx_dma.controller == DMA1 )
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
}
else
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
}
if ( wifi_spi.rx_dma.controller == DMA1 )
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
}
else
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
}
/* Enable SPI_SLAVE Periph clock */
(wifi_spi.peripheral_clock_func)( wifi_spi.peripheral_clock_reg, ENABLE );
/* Enable SYSCFG. Needed for selecting EXTI interrupt line */
RCC_APB2PeriphClockCmd( RCC_APB2Periph_SYSCFG, ENABLE );
/* Setup the interrupt input for WLAN_IRQ */
platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], INPUT_HIGH_IMPEDANCE );
platform_gpio_irq_enable( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, 0 );
/* Setup SPI slave select GPIOs */
platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_CS], OUTPUT_PUSH_PULL );
platform_gpio_output_high( &wifi_spi_pins[WIFI_PIN_SPI_CS] );
/* Setup the SPI lines */
for ( a = WIFI_PIN_SPI_CLK; a < WIFI_PIN_SPI_MAX; a++ )
{
platform_gpio_set_alternate_function( wifi_spi_pins[ a ].port, wifi_spi_pins[ a ].pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, wifi_spi.gpio_af );
}
#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
/* Set GPIO_B[1:0] to 01 to put WLAN module into gSPI mode */
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], OUTPUT_PUSH_PULL );
platform_gpio_output_high( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0] );
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], OUTPUT_PUSH_PULL );
platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1] );
#endif
/* Setup DMA for SPIX RX */
DMA_DeInit( wifi_spi.rx_dma.stream );
dma_init_structure.DMA_Channel = wifi_spi.rx_dma.channel;
dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &(wifi_spi.port->DR);
dma_init_structure.DMA_Memory0BaseAddr = 0;
dma_init_structure.DMA_DIR = DMA_DIR_PeripheralToMemory;
dma_init_structure.DMA_BufferSize = 0;
dma_init_structure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dma_init_structure.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
dma_init_structure.DMA_Mode = DMA_Mode_Normal;
dma_init_structure.DMA_Priority = DMA_Priority_VeryHigh;
dma_init_structure.DMA_FIFOMode = DMA_FIFOMode_Disable;
dma_init_structure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
dma_init_structure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
dma_init_structure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init( wifi_spi.rx_dma.stream, &dma_init_structure );
/* Setup DMA for SPIX TX */
DMA_DeInit( wifi_spi.tx_dma.stream );
dma_init_structure.DMA_Channel = wifi_spi.tx_dma.channel;
dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &(wifi_spi.port->DR);
dma_init_structure.DMA_Memory0BaseAddr = 0;
dma_init_structure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
dma_init_structure.DMA_BufferSize = 0;
dma_init_structure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dma_init_structure.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
dma_init_structure.DMA_Mode = DMA_Mode_Normal;
dma_init_structure.DMA_Priority = DMA_Priority_VeryHigh;
dma_init_structure.DMA_FIFOMode = DMA_FIFOMode_Disable;
dma_init_structure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
dma_init_structure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
dma_init_structure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init( wifi_spi.tx_dma.stream, &dma_init_structure );
/* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
/* otherwise FreeRTOS will not be able to mask the interrupt */
/* keep in mind that ARMCM3 interrupt priority logic is inverted, the highest value */
/* is the lowest priority */
NVIC_EnableIRQ( wifi_spi.rx_dma.irq_vector );
/* Enable DMA for TX */
SPI_I2S_DMACmd( wifi_spi.port, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE );
/* Setup SPI */
spi_init.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
spi_init.SPI_Mode = SPI_Mode_Master;
spi_init.SPI_DataSize = SPI_DataSize_8b;
spi_init.SPI_CPOL = SPI_CPOL_High;
spi_init.SPI_CPHA = SPI_CPHA_2Edge;
spi_init.SPI_NSS = SPI_NSS_Soft;
spi_init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
spi_init.SPI_FirstBit = SPI_FirstBit_MSB;
spi_init.SPI_CRCPolynomial = (uint16_t) 7;
/* Init SPI and enable it */
SPI_Init( wifi_spi.port, &spi_init );
SPI_Cmd( wifi_spi.port, ENABLE );
platform_mcu_powersave_enable();
return kNoErr;
}
platform_result_t platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* interface, const platform_uart_config_t* config, wiced_ring_buffer_t* optional_ring_buffer )
{
uint32_t uart_number;
UART_FIFO_CFG_T UARTFIFOConfigStruct;
config_uart_data_t config_uart_data;
wiced_assert( "bad argument", ( driver != NULL ) && ( interface != NULL ) && ( config != NULL ) );
Chip_Clock_EnablePeriphClock( SYSCTL_CLOCK_UART0 );
uart_number = platform_uart_get_port_number(interface->uart_base);
driver->rx_size = 0;
driver->tx_size = 0;
driver->last_transmit_result = PLATFORM_SUCCESS;
driver->last_receive_result = PLATFORM_SUCCESS;
driver->interface = (platform_uart_t*)interface;
host_rtos_init_semaphore( &driver->tx_complete );
host_rtos_init_semaphore( &driver->rx_complete );
platform_gpio_set_alternate_function( &driver->interface->tx_pin);
platform_gpio_set_alternate_function( &driver->interface->rx_pin);
/* Initialise USART peripheral */
Chip_UART_FIFOConfigStructInit( driver->interface->uart_base, &UARTFIFOConfigStruct );
Chip_UART_Init( driver->interface->uart_base );
Chip_UART_SetBaud( driver->interface->uart_base, config->baud_rate );
config_uart_data.databits = ( ( config->data_width == DATA_WIDTH_8BIT ) || ( ( config->data_width == DATA_WIDTH_7BIT ) && ( config->parity != NO_PARITY ) ) ) ? UART_DATABIT_8 : UART_DATABIT_7;
config_uart_data.stopbits = ( config->stop_bits == STOP_BITS_1 ) ? UART_STOPBIT_1 : UART_STOPBIT_2;
switch ( config->parity )
{
case NO_PARITY:
config_uart_data.parity = UART_PARITY_NONE;
break;
case EVEN_PARITY:
config_uart_data.parity = UART_PARITY_EVEN;
break;
case ODD_PARITY:
config_uart_data.parity = UART_PARITY_ODD;
break;
default:
return WICED_BADARG;
}
Chip_UART_ConfigData( driver->interface->uart_base, config_uart_data.databits, config_uart_data.parity, config_uart_data.stopbits );
Chip_UART_TxCmd( driver->interface->uart_base, ENABLE );
/* Enable receive data and line status interrupt */
/* Initialize FIFO for UART0 peripheral */
Chip_UART_FIFOConfig( driver->interface->uart_base, &UARTFIFOConfigStruct );
/* Enable UART Rx interrupt */
Chip_UART_IntConfig( driver->interface->uart_base, UART_INTCFG_RBR, ENABLE );
/* Enable UART line status interrupt */
Chip_UART_IntConfig( driver->interface->uart_base, UART_INTCFG_RLS, ENABLE );
/* Enable Interrupt for UART channel */
NVIC_DisableIRQ( uart_irq_vectors[ uart_number ] );
NVIC_ClearPendingIRQ( uart_irq_vectors[ uart_number ] );
/*Note the LPC uses 5 bits for interrupt priority levels*/
NVIC_EnableIRQ( uart_irq_vectors[ uart_number ] );
if ( optional_ring_buffer != NULL )
{
/* Note that the ring_buffer should've been initialised first */
driver->rx_buffer = optional_ring_buffer;
driver->rx_size = 0;
}
return PLATFORM_SUCCESS;
}
OSStatus host_platform_bus_init( void )
{
SDIO_InitTypeDef sdio_init_structure;
OSStatus result;
uint8_t a;
platform_mcu_powersave_disable();
result = mico_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1 );
if ( result != kNoErr )
{
return result;
}
/* Turn on SDIO IRQ */
SDIO->ICR = (uint32_t) 0xffffffff;
/* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
/* otherwise FreeRTOS will not be able to mask the interrupt */
/* keep in mind that ARMCM3 interrupt priority logic is inverted, the highest value */
/* is the lowest priority */
NVIC_EnableIRQ( SDIO_IRQ_CHANNEL );
NVIC_EnableIRQ( DMA2_3_IRQ_CHANNEL );
/* Set GPIO_B[1:0] to 00 to put WLAN module into SDIO mode */
#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], OUTPUT_PUSH_PULL );
platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0] );
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], OUTPUT_PUSH_PULL );
platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1] );
#endif
/* Setup GPIO pins for SDIO data & clock */
for ( a = WIFI_PIN_SDIO_CLK; a < WIFI_PIN_SDIO_MAX; a++ )
{
platform_gpio_set_alternate_function( wifi_sdio_pins[ a ].port, wifi_sdio_pins[ a ].pin_number, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SDIO );
}
#ifdef SDIO_1_BIT
platform_gpio_init( &wifi_sdio_pins[WIFI_PIN_SDIO_IRQ], INPUT_PULL_UP );
platform_gpio_irq_enable( &wifi_sdio_pins[WIFI_PIN_SDIO_IRQ], IRQ_TRIGGER_FALLING_EDGE, sdio_int_pin_irq_handler, 0 );
#endif
/*!< Enable the SDIO AHB Clock and the DMA2 Clock */
RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_DMA2, ENABLE );
RCC_APB2PeriphClockCmd( RCC_APB2Periph_SDIO, ENABLE );
SDIO_DeInit( );
sdio_init_structure.SDIO_ClockDiv = (uint8_t) 120; /* 0x78, clock is taken from the high speed APB bus ; */ /* About 400KHz */
sdio_init_structure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
sdio_init_structure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
sdio_init_structure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Enable;
sdio_init_structure.SDIO_BusWide = SDIO_BusWide_1b;
sdio_init_structure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
SDIO_Init( &sdio_init_structure );
SDIO_SetPowerState( SDIO_PowerState_ON );
SDIO_SetSDIOReadWaitMode( SDIO_ReadWaitMode_CLK );
SDIO_ClockCmd( ENABLE );
platform_mcu_powersave_enable();
return kNoErr;
}
OSStatus platform_spi_init( platform_spi_driver_t* driver, const platform_spi_t* peripheral, const platform_spi_config_t* config )
{
SPI_InitTypeDef spi_init;
OSStatus err;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
/* Calculate prescaler */
err = calculate_prescaler( config->speed, &spi_init.SPI_BaudRatePrescaler );
require_noerr(err, exit);
/* Configure data-width */
if ( config->bits == 8 )
{
spi_init.SPI_DataSize = SPI_DataSize_8b;
}
else if ( config->bits == 16 )
{
require_action( !(config->mode & SPI_USE_DMA), exit, err = kUnsupportedErr);
spi_init.SPI_DataSize = SPI_DataSize_16b;
}
else
{
err = kUnsupportedErr;
goto exit;
}
/* Configure MSB or LSB */
if ( config->mode & SPI_MSB_FIRST )
{
spi_init.SPI_FirstBit = SPI_FirstBit_MSB;
}
else
{
spi_init.SPI_FirstBit = SPI_FirstBit_LSB;
}
/* Configure mode CPHA and CPOL */
if ( config->mode & SPI_CLOCK_IDLE_HIGH )
{
spi_init.SPI_CPOL = SPI_CPOL_High;
}
else
{
spi_init.SPI_CPOL = SPI_CPOL_Low;
}
if ( config->mode & SPI_CLOCK_RISING_EDGE )
{
spi_init.SPI_CPHA = ( config->mode & SPI_CLOCK_IDLE_HIGH ) ? SPI_CPHA_2Edge : SPI_CPHA_1Edge;
}
else
{
spi_init.SPI_CPHA = ( config->mode & SPI_CLOCK_IDLE_HIGH ) ? SPI_CPHA_1Edge : SPI_CPHA_2Edge;
}
driver->peripheral = (platform_spi_t *)peripheral;
/* Init SPI GPIOs */
platform_gpio_set_alternate_function( peripheral->pin_clock->port, peripheral->pin_clock->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, peripheral->gpio_af );
platform_gpio_set_alternate_function( peripheral->pin_mosi->port, peripheral->pin_mosi->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, peripheral->gpio_af );
platform_gpio_set_alternate_function( peripheral->pin_miso->port, peripheral->pin_miso->pin_number, GPIO_OType_PP, GPIO_PuPd_UP, peripheral->gpio_af );
/* Init the chip select GPIO */
platform_gpio_init( config->chip_select, OUTPUT_PUSH_PULL );
platform_gpio_output_high( config->chip_select );
/* Enable SPI peripheral clock */
(peripheral->peripheral_clock_func)( peripheral->peripheral_clock_reg, ENABLE );
(peripheral->peripheral_clock_func)( peripheral->peripheral_clock_reg, ENABLE );
SPI_I2S_DeInit( peripheral->port );
spi_init.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
spi_init.SPI_Mode = SPI_Mode_Master;
spi_init.SPI_NSS = SPI_NSS_Soft;
spi_init.SPI_CRCPolynomial = 0x7; /* reset value */
SPI_CalculateCRC( peripheral->port, DISABLE );
/* Init and enable SPI */
SPI_Init( peripheral->port, &spi_init );
SPI_I2S_DMACmd( peripheral->port, SPI_I2S_DMAReq_Rx, DISABLE );
SPI_I2S_DMACmd( peripheral->port, SPI_I2S_DMAReq_Tx, DISABLE );
SPI_Cmd ( peripheral->port, ENABLE );
if ( config->mode & SPI_USE_DMA ){
DMA_DeInit( peripheral->rx_dma.stream );
DMA_DeInit( peripheral->tx_dma.stream );
if ( peripheral->tx_dma.controller == DMA1 )
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
}
else
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
}
if ( peripheral->rx_dma.controller == DMA1 )
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
}
else
{
RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
}
SPI_I2S_DMACmd( peripheral->port, SPI_I2S_DMAReq_Rx, ENABLE );
SPI_I2S_DMACmd( peripheral->port, SPI_I2S_DMAReq_Tx, ENABLE );
}
exit:
platform_mcu_powersave_enable();
return err;
}
