static void
pl310_wbinv_range(vm_paddr_t start, vm_size_t size)
{
if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
return;
PL310_LOCK(pl310_softc);
if (start & g_l2cache_align_mask) {
size += start & g_l2cache_align_mask;
start &= ~g_l2cache_align_mask;
}
if (size & g_l2cache_align_mask) {
size &= ~g_l2cache_align_mask;
size += g_l2cache_line_size;
}
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
platform_pl310_write_debug(pl310_softc, 3);
#endif
while (size > 0) {
#ifdef PL310_ERRATA_588369
if (pl310_softc->sc_rtl_revision <= CACHE_ID_RELEASE_r1p0) {
/*
* Errata 588369 says that clean + inv may keep the
* cache line if it was clean, the recommanded
* workaround is to clean then invalidate the cache
* line, with write-back and cache linefill disabled.
*/
pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
} else
#endif
pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA,
start);
start += g_l2cache_line_size;
size -= g_l2cache_line_size;
}
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
platform_pl310_write_debug(pl310_softc, 0);
#endif
pl310_cache_sync();
PL310_UNLOCK(pl310_softc);
}
static void
pl310_wbinv_all(void)
{
if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
return;
PL310_LOCK(pl310_softc);
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0 ||
pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
platform_pl310_write_debug(pl310_softc, 3);
#endif
pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_cache_sync();
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0 ||
pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
platform_pl310_write_debug(pl310_softc, 0);
#endif
PL310_UNLOCK(pl310_softc);
}
static void
pl310_wbinv_all(void)
{
if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
return;
PL310_LOCK(pl310_softc);
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0) {
int i, j;
for (i = 0; i < g_ways_assoc; i++) {
for (j = 0; j < g_way_size / g_l2cache_line_size; j++) {
pl310_write4(pl310_softc,
PL310_CLEAN_INV_LINE_IDX,
(i << 28 | j << 5));
}
}
pl310_cache_sync();
PL310_UNLOCK(pl310_softc);
return;
}
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
platform_pl310_write_debug(pl310_softc, 3);
#endif
pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_cache_sync();
#ifdef PL310_ERRATA_727915
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
platform_pl310_write_debug(pl310_softc, 0);
#endif
PL310_UNLOCK(pl310_softc);
}
static int
pl310_attach(device_t dev)
{
struct pl310_softc *sc = device_get_softc(dev);
int rid;
uint32_t cache_id, debug_ctrl;
phandle_t node;
sc->sc_dev = dev;
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->sc_mem_res == NULL)
panic("%s: Cannot map registers", device_get_name(dev));
/* Allocate an IRQ resource */
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_irq_res == NULL) {
device_printf(dev, "cannot allocate IRQ, not using interrupt\n");
}
pl310_softc = sc;
mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN);
cache_id = pl310_read4(sc, PL310_CACHE_ID);
sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) &
CACHE_ID_RELEASE_MASK;
device_printf(dev, "Part number: 0x%x, release: 0x%x\n",
(cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK,
(cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK);
/*
* Test for "arm,io-coherent" property and disable sync operation if
* platform is I/O coherent. Outer sync operations are not needed
* on coherent platform and may be harmful in certain situations.
*/
node = ofw_bus_get_node(dev);
if (OF_hasprop(node, "arm,io-coherent"))
sc->sc_io_coherent = true;
/*
* If L2 cache is already enabled then something has violated the rules,
* because caches are supposed to be off at kernel entry. The cache
* must be disabled to write the configuration registers without
* triggering an access error (SLVERR), but there's no documented safe
* procedure for disabling the L2 cache in the manual. So we'll try to
* invent one:
* - Use the debug register to force write-through mode and prevent
* linefills (allocation of new lines on read); now anything we do
* will not cause new data to come into the L2 cache.
* - Writeback and invalidate the current contents.
* - Disable the controller.
* - Restore the original debug settings.
*/
if (pl310_read4(sc, PL310_CTRL) & CTRL_ENABLED) {
device_printf(dev, "Warning: L2 Cache should not already be "
"active; trying to de-activate and re-initialize...\n");
sc->sc_enabled = 1;
debug_ctrl = pl310_read4(sc, PL310_DEBUG_CTRL);
platform_pl310_write_debug(sc, debug_ctrl |
DEBUG_CTRL_DISABLE_WRITEBACK | DEBUG_CTRL_DISABLE_LINEFILL);
pl310_set_way_sizes(sc);
pl310_wbinv_all();
platform_pl310_write_ctrl(sc, CTRL_DISABLED);
platform_pl310_write_debug(sc, debug_ctrl);
}
sc->sc_enabled = pl310_enabled;
if (sc->sc_enabled) {
platform_pl310_init(sc);
pl310_set_way_sizes(sc); /* platform init might change these */
pl310_write4(pl310_softc, PL310_INV_WAY, 0xffff);
pl310_wait_background_op(PL310_INV_WAY, 0xffff);
platform_pl310_write_ctrl(sc, CTRL_ENABLED);
device_printf(dev, "L2 Cache enabled: %uKB/%dB %d ways\n",
(g_l2cache_size / 1024), g_l2cache_line_size, g_ways_assoc);
if (bootverbose)
pl310_print_config(sc);
} else {
if (sc->sc_irq_res != NULL) {
sc->sc_ich = malloc(sizeof(*sc->sc_ich), M_DEVBUF, M_WAITOK);
sc->sc_ich->ich_func = pl310_config_intr;
sc->sc_ich->ich_arg = sc;
if (config_intrhook_establish(sc->sc_ich) != 0) {
device_printf(dev,
"config_intrhook_establish failed\n");
free(sc->sc_ich, M_DEVBUF);
return(ENXIO);
}
}
device_printf(dev, "L2 Cache disabled\n");
}
/* Set the l2 functions in the set of cpufuncs */
cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all;
cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range;
cpufuncs.cf_l2cache_inv_range = pl310_inv_range;
cpufuncs.cf_l2cache_wb_range = pl310_wb_range;
cpufuncs.cf_l2cache_drain_writebuf = pl310_drain_writebuf;
return (0);
}