/*
* Initialize the dedicated SSP unit and disable all chip selects.
* This function is called with interrupts disabled.
*/
static void
wzero3ssp_init(struct wzero3ssp_softc *sc)
{
if (sc->sc_model->sspaddr == PXA2X0_SSP1_BASE)
pxa2x0_clkman_config(CKEN_SSP2, 1);
else if (sc->sc_model->sspaddr == PXA2X0_SSP2_BASE)
pxa2x0_clkman_config(CKEN_SSP3, 1);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
/* XXX */
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH)
|| platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)) {
pxa2x0_gpio_set_function(39/*GPIO_WS003SH_XXX*/,
GPIO_OUT|GPIO_SET);
pxa2x0_gpio_set_function(GPIO_WS003SH_MAX1233_CS,
GPIO_OUT|GPIO_SET);
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) {
pxa2x0_gpio_set_function(GPIO_WS007SH_ADS7846_CS,
GPIO_OUT|GPIO_SET);
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) {
pxa2x0_gpio_set_function(GPIO_WS011SH_AK4184_CS,
GPIO_OUT|GPIO_SET);
}
}
/*
* Transmit a single data word to one of the ICs, keep the chip selected
* afterwards, and don't wait for data to be returned in SSDR. Interrupts
* must be held off until wzero3ssp_ic_stop() gets called.
*/
void
wzero3ssp_ic_start(int ic, uint32_t cmd)
{
struct wzero3ssp_softc *sc;
KASSERT(wzero3ssp_sc != NULL);
sc = wzero3ssp_sc;
mutex_enter(&sc->sc_mtx);
/* disable other ICs */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) {
if (ic != WZERO3_SSP_IC_ADS7846)
pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS);
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) {
if (ic != WZERO3_SSP_IC_AK4184_TP
&& ic != WZERO3_SSP_IC_AK4184_KEYPAD)
pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS);
}
/* activate the chosen one */
switch (ic) {
case WZERO3_SSP_IC_ADS7846:
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
WS007SH_SSCR0_ADS7846);
pxa2x0_gpio_clear_bit(GPIO_WS007SH_ADS7846_CS);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
& SSSR_TNF) != SSSR_TNF)
continue; /* poll */
break;
case WZERO3_SSP_IC_AK4184_TP:
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
WS011SH_SSCR0_AK4184_TP);
pxa2x0_gpio_clear_bit(GPIO_WS011SH_AK4184_CS);
(void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
& SSSR_TNF))
continue; /* poll */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd << 16);
while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
& SSSR_BUSY)
continue; /* poll */
break;
case WZERO3_SSP_IC_MAX1233:
case WZERO3_SSP_IC_AK4184_KEYPAD:
case WZERO3_SSP_IC_NUM:
default:
break;
}
}
static int
j720lcd_match(device_t parent, cfdata_t cf, void *aux)
{
if (!platid_match(&platid, &platid_mask_MACH_HP_JORNADA_7XX))
return 0;
if (strcmp(cf->cf_name, "j720lcd") != 0)
return 0;
return 1;
}
struct platid_data *
platid_search_data(platid_t *pid, struct platid_data *datap)
{
while (datap->mask != NULL && !platid_match(pid, datap->mask))
datap++;
if (datap->mask == NULL && datap->data == NULL)
return (NULL);
return (datap);
}
static int
psh3pwr_match(device_t parent, struct cfdata *cfp, void *aux)
{
if (!platid_match(&platid, &platid_mask_MACH_HITACHI_PERSONA))
return 0;
if (strcmp(cfp->cf_name, "psh3pwr") != 0)
return 0;
return 1;
}
static const struct wzero3kbd_model *
wzero3kbd_lookup(void)
{
const struct wzero3kbd_model *model;
for (model = wzero3kbd_table; model->platid != NULL; model++) {
if (platid_match(&platid, model->platid)) {
return model;
}
}
return NULL;
}
BOOL
SHBoot::setup()
{
struct HpcMenuInterface::HpcMenuPreferences &pref = HPC_PREFERENCE;
platid_t platid;
platid.dw.dw0 = pref.platid_hi;
platid.dw.dw1 = pref.platid_lo;
if (platid_match(&platid, &platid_mask_CPU_SH_3_7709)) {
args.architecture = ARCHITECTURE_SH3_7709;
} else if (platid_match(&platid, &platid_mask_CPU_SH_3_7709A)) {
args.architecture = ARCHITECTURE_SH3_7709A;
} else if (platid_match(&platid, &platid_mask_CPU_SH_4_7750)) {
args.architecture = ARCHITECTURE_SH4_7750;
} else {
DPRINTF((TEXT("CPU not supported.")));
return FALSE;
}
return super::setup();
}
int
hpcioman_match(struct device *parent, struct cfdata *cf, void *aux)
{
struct hpcio_attach_args *haa = aux;
platid_mask_t mask;
if (strcmp(haa->haa_busname, HPCIO_BUSNAME))
return (0);
/* select platform */
mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]);
return (platid_match(&platid, &mask));
}
void
hd64461uartcninit(struct consdev *cp)
{
struct com_regs regs;
hd64461uart_init();
HD64461UART_INIT_REGS(regs, hd64461uart_chip.io_tag, 0x0, 0x0);
comcnattach1(®s, COMCN_SPEED, COM_FREQ, COM_TYPE_NORMAL, CONMODE);
hd64461uart_chip.console = 1;
/* Don't stop to suply AFECK */
if (platid_match(&platid, &platid_mask_MACH_HITACHI_PERSONA))
use_afeck = 1;
}
FrameBufferInfo::FrameBufferInfo(uint32_t cpu, uint32_t machine)
{
struct framebuffer_info *tab = _table;
platid_mask_t target, entry;
framebuffer_info *alt = 0;
// get current bpp.
HDC hdc = GetDC(0);
int bpp = GetDeviceCaps(hdc, BITSPIXEL);
ReleaseDC(0, hdc);
target.dw.dw0 = cpu;
target.dw.dw1 = machine;
// search apriori setting if any.
for (; tab->cpu; tab++) {
entry.dw.dw0 = tab->cpu;
entry.dw.dw1 = tab->machine;
if (platid_match(&target, &entry)) {
if (tab->bpp == bpp) {
_fb = tab;
return;
} else {
alt = tab;
}
}
}
// use alternative framebuffer setting, if any.
if (alt) {
_fb = alt;
return;
}
// no apriori setting. fill default.
memset(&_default, 0, sizeof(struct framebuffer_info));
_default.cpu = cpu;
_default.machine = machine;
hdc = GetDC(0);
_default.bpp = bpp;
_default.width = GetDeviceCaps(hdc, HORZRES);
_default.height = GetDeviceCaps(hdc, VERTRES);
ReleaseDC(0, hdc);
_fb = &_default;
}
STATIC void
hd64461uart_attach(device_t parent, device_t self, void *aux)
{
struct hd64461_attach_args *ha = aux;
struct hd64461uart_softc *sc = device_private(self);
struct com_softc *csc = &sc->sc_com;
uint16_t r16, or16;
bus_space_handle_t ioh;
csc->sc_dev = self;
sc->sc_chip = &hd64461uart_chip;
sc->sc_module_id = ha->ha_module_id;
if (!sc->sc_chip->console)
hd64461uart_init();
bus_space_map(sc->sc_chip->io_tag, 0x0, 8, 0, &ioh);
csc->sc_frequency = COM_FREQ;
HD64461UART_INIT_REGS(csc->sc_regs, sc->sc_chip->io_tag, ioh, 0x0);
/* switch port to UART */
/* supply clock */
r16 = or16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16);
r16 &= ~HD64461_SYSSTBCR_SURTSD;
if (platid_match(&platid, &platid_mask_MACH_HITACHI_PERSONA))
r16 &= ~(HD64461_SYSSTBCR_SAFECKE_IST |
HD64461_SYSSTBCR_SAFECKE_OST);
hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16);
/* sanity check */
if (!com_probe_subr(&csc->sc_regs)) {
aprint_error(": device problem. don't attach.\n");
/* restore old clock */
hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, or16);
return;
}
com_attach_subr(csc);
hd6446x_intr_establish(HD64461_INTC_UART, IST_LEVEL, IPL_TTY,
comintr, csc);
}
void *
platid_search(platid_t *pid, void *base, int nmemb, int size)
{
int i, match_level, res;
void *match;
match_level = 0;
match = NULL;
for (i = 0; i < nmemb; i++) {
res = platid_match(pid, *(platid_mask_t**)base);
if (match_level < res) {
match_level = res;
match = base;
}
base = (char *)base + size;
}
return (match);
}
int
vrisabmatch(device_t parent, cfdata_t match, void *aux)
{
struct hpcio_attach_args *haa = aux;
platid_mask_t mask;
int n;
if (strcmp(haa->haa_busname, match->cf_name))
return (0);
if (match->cf_loc[HPCIOIFCF_PLATFORM] == HPCIOIFCF_PLATFORM_DEFAULT)
return (1);
mask = PLATID_DEREF(match->cf_loc[HPCIOIFCF_PLATFORM]);
if ((n = platid_match(&platid, &mask)) != 0)
return (n + 2);
return (0);
}
int
mainbus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
{
struct mainbus_attach_args *ma = (void *)aux;
int locator = cf->cf_loc[MAINBUSCF_PLATFORM];
/* check device name */
if (strcmp(ma->ma_name, cf->cf_name) != 0)
return (0);
/* check platform ID in config file */
if (locator != MAINBUSCF_PLATFORM_DEFAULT &&
!platid_match(&platid, PLATID_DEREFP(locator)))
return (0);
/* attach device */
if (config_match(parent, cf, ma))
config_attach(parent, cf, ma, mainbus_print);
return (0);
}
int
hd64461uart_kgdb_init(void)
{
struct com_regs regs;
if (strcmp(kgdb_devname, "hd64461uart") != 0)
return 1;
if (hd64461uart_chip.console)
return 1; /* can't share with console */
hd64461uart_init();
HD64461UART_INIT_REGS(regs, hd64461uart_chip.io_tag, NULL, 0x0);
if (com_kgdb_attach1(®s,
kgdb_rate, COM_FREQ, COM_TYPE_NORMAL, CONMODE) != 0) {
printf("%s: KGDB console open failed.\n", __func__);
return 1;
}
if (platid_match(&platid, &platid_mask_MACH_HITACHI_PERSONA))
use_afeck = 1;
return 0;
}
void
machine_startup(int argc, char *argv[], struct bootinfo *bi)
{
extern char edata[], end[];
vaddr_t kernend;
size_t symbolsize;
int i;
char *p;
/*
* this routines stack is never polluted since stack pointer
* is lower than kernel text segment, and at exiting, stack pointer
* is changed to proc0.
*/
struct kloader_bootinfo kbi;
/* Symbol table size */
symbolsize = 0;
if (memcmp(&end, ELFMAG, SELFMAG) == 0) {
Elf_Ehdr *eh = (void *)end;
Elf_Shdr *sh = (void *)(end + eh->e_shoff);
for(i = 0; i < eh->e_shnum; i++, sh++)
if (sh->sh_offset > 0 &&
(sh->sh_offset + sh->sh_size) > symbolsize)
symbolsize = sh->sh_offset + sh->sh_size;
}
/* Clear BSS */
memset(edata, 0, end - edata);
/* Setup bootinfo */
bootinfo = &kbi.bootinfo;
memcpy(bootinfo, bi, sizeof(struct bootinfo));
if (bootinfo->magic == BOOTINFO_MAGIC) {
platid.dw.dw0 = bootinfo->platid_cpu;
platid.dw.dw1 = bootinfo->platid_machine;
}
/* CPU initialize */
if (platid_match(&platid, &platid_mask_CPU_SH_3))
sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
else if (platid_match(&platid, &platid_mask_CPU_SH_4))
sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
/* Start to determine heap area */
kernend = (vaddr_t)sh3_round_page(end + symbolsize);
/* Setup bootstrap options */
makebootdev("wd0"); /* default boot device */
boothowto = 0;
for (i = 1; i < argc; i++) { /* skip 1st arg (kernel name). */
char *cp = argv[i];
switch (*cp) {
case 'b':
/* boot device: -b=sd0 etc. */
p = cp + 2;
#ifdef NFS
if (strcmp(p, "nfs") == 0)
mountroot = nfs_mountroot;
else
makebootdev(p);
#else /* NFS */
makebootdev(p);
#endif /* NFS */
break;
default:
BOOT_FLAG(*cp, boothowto);
break;
}
}
#ifdef MFS
/*
* Check to see if a mini-root was loaded into memory. It resides
* at the start of the next page just after the end of BSS.
*/
if (boothowto & RB_MINIROOT) {
size_t fssz;
fssz = sh3_round_page(mfs_initminiroot((void *)kernend));
#ifdef MEMORY_DISK_DYNAMIC
md_root_setconf((caddr_t)kernend, fssz);
#endif
kernend += fssz;
}
#endif /* MFS */
/* Console */
consinit();
#ifdef HPC_DEBUG_LCD
dbg_lcd_test();
#endif
/* copy boot parameter for kloader */
kloader_bootinfo_set(&kbi, argc, argv, bi, TRUE);
/* Find memory cluster. and load to UVM */
physmem = mem_cluster_init(SH3_P1SEG_TO_PHYS(kernend));
_DPRINTF("total memory = %dMbyte\n", (int)(sh3_ptob(physmem) >> 20));
mem_cluster_load();
/* Initialize proc0 u-area */
sh_proc0_init();
/* Initialize pmap and start to address translation */
pmap_bootstrap();
/* Debugger. */
#ifdef DDB
if (symbolsize) {
ddb_init(symbolsize, &end, end + symbolsize);
_DPRINTF("symbol size = %d byte\n", symbolsize);
}
if (boothowto & RB_KDB)
Debugger();
#endif /* DDB */
#ifdef KGDB
if (boothowto & RB_KDB) {
if (kgdb_dev == NODEV) {
printf("no kgdb console.\n");
} else {
kgdb_debug_init = 1;
kgdb_connect(1);
}
}
#endif /* KGDB */
/* Jump to main */
__asm__ __volatile__(
"jmp @%0;"
"mov %1, sp"
:: "r"(main),"r"(proc0.p_md.md_pcb->pcb_sf.sf_r7_bank));
/* NOTREACHED */
while (1)
;
}
static void
vrc4172pci_attach(struct device *parent, struct device *self, void *aux)
{
struct vrc4172pci_softc *sc = (struct vrc4172pci_softc *)self;
pci_chipset_tag_t pc = &sc->sc_pc;
struct vrip_attach_args *va = aux;
#if NPCI > 0
struct pcibus_attach_args pba;
#endif
sc->sc_iot = va->va_iot;
if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 0,
&sc->sc_ioh)) {
printf(": couldn't map io space\n");
return;
}
printf("\n");
#ifdef VRC4172PCI_MCR700_SUPPORT
if (platid_match(&platid, &platid_mask_MACH_NEC_MCR_700) ||
platid_match(&platid, &platid_mask_MACH_NEC_MCR_700A) ||
platid_match(&platid, &platid_mask_MACH_NEC_MCR_730) ||
platid_match(&platid, &platid_mask_MACH_NEC_MCR_730A)) {
/* power USB controller on MC-R700 */
sc->sc_iochip = va->va_gpio_chips[VRIP_IOCHIP_VRGIU];
hpcio_portwrite(sc->sc_iochip, 45, 1);
sc->sc_fake_baseaddr = 0x0afe0000;
#if 0
sc->sc_ih = hpcio_intr_establish(sc->sc_iochip, 1,
HPCIO_INTR_EDGE|HPCIO_INTR_HOLD,
vrc4172pci_mcr700_intr, sc);
#endif
}
#endif /* VRC4172PCI_MCR700_SUPPORT */
pc->pc_dev = &sc->sc_dev;
pc->pc_attach_hook = vrc4172pci_attach_hook;
pc->pc_bus_maxdevs = vrc4172pci_bus_maxdevs;
pc->pc_bus_devorder = vrc4172pci_bus_devorder;
pc->pc_make_tag = vrc4172pci_make_tag;
pc->pc_decompose_tag = vrc4172pci_decompose_tag;
pc->pc_conf_read = vrc4172pci_conf_read;
pc->pc_conf_write = vrc4172pci_conf_write;
pc->pc_intr_map = vrc4172pci_intr_map;
pc->pc_intr_string = vrc4172pci_intr_string;
pc->pc_intr_evcnt = vrc4172pci_intr_evcnt;
pc->pc_intr_establish = vrc4172pci_intr_establish;
pc->pc_intr_disestablish = vrc4172pci_intr_disestablish;
#if 0
{
int i;
for (i = 0; i < 2; i++)
printf("%s: ID_REG(0, 0, %d) = 0x%08x\n",
sc->sc_dev.dv_xname, i,
pci_conf_read(pc, pci_make_tag(pc, 0, 0, i),
PCI_ID_REG));
}
#endif
#if NPCI > 0
memset(&pba, 0, sizeof(pba));
pba.pba_iot = sc->sc_iot;
pba.pba_memt = sc->sc_iot;
pba.pba_dmat = &hpcmips_default_bus_dma_tag.bdt;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY;
pba.pba_pc = pc;
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
static void
wzero3kbd_attach(device_t parent, device_t self, void *aux)
{
struct wzero3kbd_softc *sc = device_private(self);
struct pxaip_attach_args *pxa = (struct pxaip_attach_args *)aux;
struct hpckbd_attach_args haa;
const struct wzero3kbd_model *model;
sc->sc_dev = self;
model = wzero3kbd_lookup();
if (model == NULL) {
aprint_error(": unknown model\n");
return;
}
aprint_normal(": keyboard\n");
aprint_naive("\n");
sc->sc_key_pin = model->key_pin;
sc->sc_power_pin = model->power_pin;
sc->sc_reset_pin = model->reset_pin;
sc->sc_ncolumn = model->ncolumn;
sc->sc_nrow = model->nrow;
sc->sc_iot = pxa->pxa_iot;
if (bus_space_map(sc->sc_iot, PXA2X0_CS2_START, REGMAPSIZE, 0,
&sc->sc_ioh)) {
aprint_error_dev(self, "couldn't map registers.\n");
return;
}
sc->sc_okeystat = malloc(sc->sc_nrow * sc->sc_ncolumn, M_DEVBUF,
M_NOWAIT | M_ZERO);
sc->sc_keystat = malloc(sc->sc_nrow * sc->sc_ncolumn, M_DEVBUF,
M_NOWAIT | M_ZERO);
if (sc->sc_okeystat == NULL || sc->sc_keystat == NULL) {
aprint_error_dev(self, "couldn't alloc memory.\n");
if (sc->sc_okeystat)
free(sc->sc_okeystat, M_DEVBUF);
if (sc->sc_keystat)
free(sc->sc_keystat, M_DEVBUF);
return;
}
sc->sc_if.hii_ctx = sc;
sc->sc_if.hii_establish = wzero3kbd_input_establish;
sc->sc_if.hii_poll = wzero3kbd_poll;
/* Attach console if not using serial. */
if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL))
hpckbd_cnattach(&sc->sc_if);
/* Install interrupt handler. */
if (sc->sc_key_pin >= 0) {
pxa2x0_gpio_set_function(sc->sc_key_pin, GPIO_IN);
sc->sc_key_ih = pxa2x0_gpio_intr_establish(sc->sc_key_pin,
IST_EDGE_BOTH, IPL_TTY, wzero3kbd_intr, sc);
if (sc->sc_key_ih == NULL) {
aprint_error_dev(sc->sc_dev,
"couldn't establish key interrupt\n");
}
} else {
sc->sc_interval = KEY_INTERVAL / (1000 / hz);
if (sc->sc_interval < 1)
sc->sc_interval = 1;
callout_init(&sc->sc_keyscan_ch, 0);
callout_reset(&sc->sc_keyscan_ch, sc->sc_interval,
wzero3kbd_tick, sc);
}
/* power key */
if (sc->sc_power_pin >= 0) {
pxa2x0_gpio_set_function(sc->sc_power_pin, GPIO_IN);
sc->sc_power_ih = pxa2x0_gpio_intr_establish(
sc->sc_power_pin, IST_EDGE_BOTH, IPL_TTY,
wzero3kbd_power_intr, sc);
if (sc->sc_power_ih == NULL) {
aprint_error_dev(sc->sc_dev,
"couldn't establish power key interrupt\n");
}
}
/* reset button */
if (sc->sc_reset_pin >= 0) {
pxa2x0_gpio_set_function(sc->sc_reset_pin, GPIO_IN);
sc->sc_reset_ih = pxa2x0_gpio_intr_establish(
sc->sc_reset_pin, IST_EDGE_BOTH, IPL_TTY,
wzero3kbd_reset_intr, sc);
if (sc->sc_reset_ih == NULL) {
aprint_error_dev(sc->sc_dev,
"couldn't establish reset key interrupt\n");
}
sc->sc_smpsw.smpsw_name = device_xname(self);
sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_RESET;
if (sysmon_pswitch_register(&sc->sc_smpsw) != 0) {
aprint_error_dev(sc->sc_dev,
"unable to register reset event handler\n");
}
}
/* Attach hpckbd. */
haa.haa_ic = &sc->sc_if;
config_found(self, &haa, hpckbd_print);
#if defined(KEYTEST) || defined(KEYTEST2) || defined(KEYTEST3) || defined(KEYTEST4) || defined(KEYTEST5)
sc->sc_test_ih = NULL;
sc->sc_test_pin = -1;
sc->sc_nouse_pin = -1;
sc->sc_nouse_pin2 = -1;
sc->sc_nouse_pin3 = -1;
sc->sc_bit = 0x01;
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH)
|| platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)) {
sc->sc_nouse_pin = GPIO_WS003SH_SD_DETECT; /* SD_DETECT */
sc->sc_nouse_pin2 = 86; /* Vsync? */
sc->sc_nouse_pin3 = 89; /* RESET? */
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) {
sc->sc_nouse_pin = GPIO_WS007SH_SD_DETECT; /* SD_DETECT */
sc->sc_nouse_pin2 = 77; /* Vsync? */
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) {
sc->sc_nouse_pin = GPIO_WS011SH_SD_DETECT; /* SD_DETECT */
sc->sc_nouse_pin2 = 77; /* Vsync? */
}
if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS020SH)) {
sc->sc_nouse_pin = GPIO_WS020SH_SD_DETECT; /* SD_DETECT */
sc->sc_nouse_pin2 = 77; /* Vsync? */
}
#ifdef KEYTEST
for (sc->sc_test_pin = 2; sc->sc_test_pin < PXA270_GPIO_NPINS; sc->sc_test_pin++) {
if (sc->sc_test_pin != sc->sc_nouse_pin
&& sc->sc_test_pin != sc->sc_nouse_pin2
&& sc->sc_test_pin != sc->sc_nouse_pin3
&& sc->sc_test_pin != sc->sc_key_pin
&& sc->sc_test_pin != sc->sc_power_pin
&& sc->sc_test_pin != sc->sc_reset_pin
&& GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(sc->sc_test_pin)))
break;
}
if (sc->sc_test_pin < PXA270_GPIO_NPINS) {
printf("GPIO_IN: GPIO pin #%d\n", sc->sc_test_pin);
sc->sc_test_ih = pxa2x0_gpio_intr_establish(sc->sc_test_pin,
IST_EDGE_BOTH, IPL_TTY, wzero3kbd_intr2, sc);
} else {
sc->sc_test_pin = -1;
}
#endif
#ifdef KEYTEST3
{
int i;
printf("pin: ");
for (i = 0; i < PXA270_GPIO_NPINS; i++) {
if (i == sc->sc_nouse_pin
|| i == sc->sc_nouse_pin2
|| i == sc->sc_nouse_pin3
|| i == sc->sc_key_pin
|| i == sc->sc_power_pin
|| i == sc->sc_reset_pin)
continue;
printf("%d, ", i);
if (GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(i))) {
pxa2x0_gpio_intr_establish(i, IST_EDGE_BOTH,
IPL_TTY, wzero3kbd_intr3, (void *)(long)i);
}
}
}
#endif
#ifdef KEYTEST4
for (sc->sc_test_pin = 2; sc->sc_test_pin < PXA270_GPIO_NPINS; sc->sc_test_pin++) {
if (sc->sc_test_pin != sc->sc_nouse_pin
&& sc->sc_test_pin != sc->sc_nouse_pin2
&& sc->sc_test_pin != sc->sc_nouse_pin3
&& sc->sc_test_pin != sc->sc_key_pin
&& sc->sc_test_pin != sc->sc_power_pin
&& sc->sc_test_pin != sc->sc_reset_pin
&& GPIO_IS_GPIO_OUT(pxa2x0_gpio_get_function(sc->sc_test_pin)))
break;
}
if (sc->sc_test_pin < PXA270_GPIO_NPINS) {
printf("GPIO_OUT: GPIO pin #%d\n", sc->sc_test_pin);
} else {
sc->sc_test_pin = -1;
}
#endif
#ifdef KEYTEST5
sc->sc_test_pin = 0x00;
sc->sc_bit = 0x01;
#endif
#endif
}
void
hd64461pcmcia_power(int ch, enum pcmcia_voltage vol, int on)
{
#define VCC0_ON() \
do { \
r = hd64461_reg_read_1(gcr); \
r |= HD64461_PCCGCR_VCC0; \
hd64461_reg_write_1(gcr, r); \
} while (/*CONSTCOND*/0)
#define VCC0_OFF() \
do { \
r = hd64461_reg_read_1(gcr); \
r &= ~HD64461_PCCGCR_VCC0; \
hd64461_reg_write_1(gcr, r); \
} while (/*CONSTCOND*/0)
#define VCC1_ON() \
do { \
r = hd64461_reg_read_1(scr); \
r |= HD64461_PCCSCR_VCC1; \
hd64461_reg_write_1(scr, r); \
} while (/*CONSTCOND*/0)
#define VCC1_OFF() \
do { \
r = hd64461_reg_read_1(scr); \
r &= ~HD64461_PCCSCR_VCC1; \
hd64461_reg_write_1(scr, r); \
} while (/*CONSTCOND*/0)
bus_addr_t isr, gcr, scr;
u_int8_t r;
isr = HD64461_PCCISR(ch);
gcr = HD64461_PCCGCR(ch);
scr = HD64461_PCCSCR(ch);
/* 3.3 V */
if (vol == V_3_3) {
if (ch == 1) {
if (on) {
VCC0_OFF();
VCC1_OFF();
} else {
VCC0_ON();
VCC1_ON();
}
} else {
if (on) {
VCC0_ON();
VCC1_OFF();
} else {
VCC0_OFF();
VCC1_ON();
}
}
return;
}
/* 5 V */
if (platid_match(&platid, &platid_mask_MACH_HP)) {
if (on) {
VCC0_OFF();
VCC1_OFF();
} else {
VCC0_ON();
VCC1_ON();
}
return;
} else if (platid_match(&platid, &platid_mask_MACH_HITACHI)) {
if (on) {
VCC0_OFF();
VCC1_ON();
} else {
VCC0_ON();
VCC1_OFF();
}
return;
}
/* x.x V, y.y V */
printf("x.x/y.y V not supported.\n");
#undef VCC0_ON
#undef VCC0_OFF
#undef VCC1_ON
#undef VCC1_OFF
}
static void
sed1356_attach(struct device *parent, struct device *self, void *aux)
{
struct sed1356_softc *sc = (struct sed1356_softc *)self;
struct hpcfb_attach_args ha;
int console = (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) ? 0 : 1;
if (attach_flag) {
panic("%s(%d): sed1356 attached twice", __FILE__, __LINE__);
}
attach_flag = 1;
if (sed1356_init(&sc->sc_fbconf) != 0) {
/* just return so that hpcfb will not be attached */
return;
}
printf("\n");
sc->sc_iot = &sa11x0_bs_tag;
sc->sc_parent = (struct sa11x0_softc *)parent;
if (bus_space_map(sc->sc_iot, (bus_addr_t)bootinfo->fb_addr & ~0x3fffff,
0x200, 0, &sc->sc_regh)) {
printf("%s: unable to map register\n", sc->sc_dev.dv_xname);
return;
}
printf("%s: Epson SED1356", sc->sc_dev.dv_xname);
if (console) {
printf(", console");
}
printf("\n");
printf("%s: framebuffer address: 0x%08lx\n",
sc->sc_dev.dv_xname, (u_long)bootinfo->fb_addr);
/* Add a suspend hook to power saving */
sc->sc_powerstate = 0;
sc->sc_powerhook = powerhook_establish(self->dv_xname,
sed1356_power, sc);
if (sc->sc_powerhook == NULL)
printf("%s: WARNING: unable to establish power hook\n",
sc->sc_dev.dv_xname);
/* Initialize backlight brightness and lcd contrast */
sc->sc_lcd_inited = 0;
sed1356_init_brightness(sc, 1);
sed1356_init_contrast(sc, 1);
sed1356_init_backlight(sc, 1);
if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0)
panic("sed1356_attach: cannot init fb console");
ha.ha_console = console;
ha.ha_accessops = &sed1356_ha;
ha.ha_accessctx = sc;
ha.ha_curfbconf = 0;
ha.ha_nfbconf = 1;
ha.ha_fbconflist = &sc->sc_fbconf;
ha.ha_curdspconf = 0;
ha.ha_ndspconf = 1;
ha.ha_dspconflist = &sc->sc_dspconf;
/* XXX */
if (platid_match(&platid, &platid_mask_MACH_HP_JORNADA_7XX)) {
config_hook(CONFIG_HOOK_POWERCONTROL,
CONFIG_HOOK_POWERCONTROL_LCDLIGHT,
CONFIG_HOOK_SHARE, j720lcd_power, sc);
}
config_found(self, &ha, hpcfbprint);
}
