/** * \brief Enable USB clock. * * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1 * is hidden in this implementation. Use div as div effective value. * * \param pll_id Source of the USB clock. * \param div Actual clock divisor. Must be superior to 0. */ void sysclk_enable_usb(void) { Assert(CONFIG_USBCLK_DIV > 0); #ifdef CONFIG_PLL0_SOURCE if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); pmc_enable_udpck(); return; } #endif #ifdef CONFIG_PLL1_SOURCE if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL1) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1); pmc_enable_udpck(); return; } #endif }
/** * \brief Enable USB clock. * * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1 * is hidden in this implementation. Use div as div effective value. * * \param pll_id Source of the USB clock. * \param div Actual clock diviser. Must be superior to 0. */ void sysclk_enable_usb(void) { Assert(CONFIG_USBCLK_DIV > 0); switch (CONFIG_USBCLK_SOURCE) { #ifdef CONFIG_PLL0_SOURCE case USBCLK_SRC_PLL0: { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); pmc_enable_udpck(); break; } #endif #ifdef CONFIG_PLL1_SOURCE case USBCLK_SRC_PLL1: { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1); pmc_enable_udpck(); break; } #endif } }
/** * \brief Configure clock for coprocessor. */ static void sysclk_configure_cpclk(void) { #if ((CONFIG_CPCLK_PRES < CPCLK_PRES_MIN) || (CONFIG_CPCLK_PRES > CPCLK_PRES_MAX)) #error Invalid CONFIG_CPCLK_PRES setting. #endif /* Assert coprocessor reset and reset its peripheral */ RSTC->RSTC_CPMR = RSTC_CPMR_CPKEY(0x5Au); #ifdef CONFIG_PLL0_SOURCE if ((CONFIG_CPCLK_SOURCE == CPCLK_SRC_PLLACK) && (pll_is_locked(0) == 0)) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); } #endif #ifdef CONFIG_PLL1_SOURCE if ((CONFIG_CPCLK_SOURCE == CPCLK_SRC_PLLBCK) && (pll_is_locked(1) == 0)) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); } #endif uint32_t read_reg; /* Enables Coprocessor Bus Master Clock */ PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD; /* Enables the Coprocessor Clocks */ PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; /* Set coprocessor clock prescaler and source */ read_reg = REG_PMC_MCKR; read_reg &= ~PMC_MCKR_CPPRES_Msk; read_reg |= PMC_MCKR_CPPRES(CONFIG_CPCLK_PRES - 1); REG_PMC_MCKR = read_reg; /* Choose coprocessor main clock source */ read_reg = REG_PMC_MCKR; read_reg &= ~PMC_MCKR_CPCSS_Msk; read_reg |= (CONFIG_CPCLK_SOURCE << PMC_MCKR_CPCSS_Pos); REG_PMC_MCKR = read_reg; /* Release coprocessor peripheral reset */ RSTC->RSTC_CPMR |= (RSTC_CPMR_CPKEY(0x5Au) | RSTC_CPMR_CPEREN); /* Enable Core 1 SRAM1 and SRAM2 memories */ pmc_enable_periph_clk(42); /* ID_SRAM1_2 */ }
/** * \brief Test Pll and DFLL (if have) * * This test enables pll/dfll source clock, sets its mul and div * factor, and then enables it. Check if it's locked after max * startup time. * * \param test Current test case. */ static void run_pll_dfll_test(const struct test_case *test) { uint32_t wait; bool status; /* avoid Cppcheck Warning */ UNUSED(wait); UNUSED(status); #if (defined CONFIG_PLL0_SOURCE) || (defined CONFIG_PLL1_SOURCE) struct pll_config pllcfg; #endif #ifdef CONFIG_PLL0_SOURCE pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, PLL0); for (wait = 0; wait < PLL_MAX_STARTUP_CYCLES; wait++) { //waiting PLL0 lock __asm__("nop"); }; status = pll_is_locked(PLL0); test_assert_true(test, status, "PLL0 can't be locked"); #endif #ifdef CONFIG_PLL1_SOURCE pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, PLL1); for (wait = 0; wait < PLL_MAX_STARTUP_CYCLES; wait++) { //waiting PLL1 lock __asm__("nop"); }; status = pll_is_locked(PLL1); test_assert_true(test, status, "PLL1 can't be locked"); #endif #ifdef CONFIG_DFLL0_SOURCE struct dfll_config dfllcfg; osc_enable(OSC_ID_RCSYS); osc_wait_ready(OSC_ID_RCSYS); dfll_config_defaults(&dfllcfg, 0); dfll_enable_closed_loop(&dfllcfg, 0); for (wait = 0; wait < DFLL_MAX_LOCK_CYCLES; wait++) { //waiting DFLL lock __asm__("nop"); }; status = dfll_is_fine_locked(0); test_assert_true(test, status, "DFLL can't be locked"); #endif }
/** * \brief Enable USB clock. * * \note The SAM3U UDP hardware interprets div as div+1. For readability the * hardware div+1 is hidden in this implementation. Use div as div * effective value. * * \param pll_id Source of the USB clock. * \param div Actual clock divisor. Must be superior to 0. */ void sysclk_enable_usb(void) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); }
void sysclk_init(void) { struct pll_config pllcfg; /* Set a flash wait state depending on the new cpu frequency */ system_init_flash(sysclk_get_cpu_hz()); /* Config system clock setting */ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { osc_enable(OSC_SLCK_32K_RC); osc_wait_ready(OSC_SLCK_32K_RC); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { osc_enable(OSC_SLCK_32K_XTAL); osc_wait_ready(OSC_SLCK_32K_XTAL); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { osc_enable(OSC_SLCK_32K_BYPASS); osc_wait_ready(OSC_SLCK_32K_BYPASS); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { osc_enable(OSC_MAINCK_8M_RC); osc_wait_ready(OSC_MAINCK_8M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { osc_enable(OSC_MAINCK_12M_RC); osc_wait_ready(OSC_MAINCK_12M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { osc_enable(OSC_MAINCK_XTAL); osc_wait_ready(OSC_MAINCK_XTAL); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { osc_enable(OSC_MAINCK_BYPASS); osc_wait_ready(OSC_MAINCK_BYPASS); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } #ifdef CONFIG_PLL0_SOURCE else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { pll_enable_source(CONFIG_PLL0_SOURCE); // Source is mainck, select source for mainck if (CONFIG_PLL0_SOURCE == PLL_SRC_MAINCK_4M_RC || CONFIG_PLL0_SOURCE == PLL_SRC_MAINCK_8M_RC || CONFIG_PLL0_SOURCE == PLL_SRC_MAINCK_12M_RC) { pmc_mainck_osc_select(0); while(!pmc_osc_is_ready_mainck()); # ifndef CONFIG_PLL1_SOURCE pmc_osc_disable_main_xtal(); # endif } else if (CONFIG_PLL0_SOURCE == PLL_SRC_MAINCK_XTAL || CONFIG_PLL0_SOURCE == PLL_SRC_MAINCK_BYPASS) { pmc_mainck_osc_select(CKGR_MOR_MOSCSEL); while(!pmc_osc_is_ready_mainck()); } pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); } #endif else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); } /* Update the SystemFrequency variable */ SystemCoreClockUpdate(); #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) /* Signal that the internal frequencies are setup */ sysclk_initialized = 1; #endif }
void sysclk_init(void) { /* Set flash wait state to max in case the below clock switching. */ system_init_flash(CHIP_FREQ_CPU_MAX); /* Config system clock setting */ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { osc_enable(OSC_SLCK_32K_RC); osc_wait_ready(OSC_SLCK_32K_RC); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { osc_enable(OSC_SLCK_32K_XTAL); osc_wait_ready(OSC_SLCK_32K_XTAL); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { osc_enable(OSC_SLCK_32K_BYPASS); osc_wait_ready(OSC_SLCK_32K_BYPASS); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { osc_enable(OSC_MAINCK_8M_RC); osc_wait_ready(OSC_MAINCK_8M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { osc_enable(OSC_MAINCK_12M_RC); osc_wait_ready(OSC_MAINCK_12M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { osc_enable(OSC_MAINCK_XTAL); osc_wait_ready(OSC_MAINCK_XTAL); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { osc_enable(OSC_MAINCK_BYPASS); osc_wait_ready(OSC_MAINCK_BYPASS); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); } #ifdef CONFIG_PLL0_SOURCE else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { struct pll_config pllcfg; pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); } #endif /* Update the SystemFrequency variable */ SystemCoreClockUpdate(); /* Set a flash wait state depending on the new cpu frequency */ system_init_flash(sysclk_get_cpu_hz()); #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) /* Signal that the internal frequencies are setup */ sysclk_initialized = 1; #endif }
void sysclk_init(void) { struct pll_config pllcfg; /* Set a flash wait state depending on the new cpu frequency */ system_init_flash(sysclk_get_cpu_hz()); /* Config system clock setting */ switch (CONFIG_SYSCLK_SOURCE) { case SYSCLK_SRC_SLCK_RC: osc_enable(OSC_SLCK_32K_RC); osc_wait_ready(OSC_SLCK_32K_RC); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_SLCK_XTAL: osc_enable(OSC_SLCK_32K_XTAL); osc_wait_ready(OSC_SLCK_32K_XTAL); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_SLCK_BYPASS: osc_enable(OSC_SLCK_32K_BYPASS); osc_wait_ready(OSC_SLCK_32K_BYPASS); pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_MAINCK_4M_RC: /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ break; case SYSCLK_SRC_MAINCK_8M_RC: osc_enable(OSC_MAINCK_8M_RC); osc_wait_ready(OSC_MAINCK_8M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_MAINCK_12M_RC: osc_enable(OSC_MAINCK_12M_RC); osc_wait_ready(OSC_MAINCK_12M_RC); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_MAINCK_XTAL: osc_enable(OSC_MAINCK_XTAL); osc_wait_ready(OSC_MAINCK_XTAL); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); break; case SYSCLK_SRC_MAINCK_BYPASS: osc_enable(OSC_MAINCK_BYPASS); osc_wait_ready(OSC_MAINCK_BYPASS); pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); break; #ifdef CONFIG_PLL0_SOURCE case SYSCLK_SRC_PLLACK: pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, 0); pll_wait_for_lock(0); pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); break; #endif case SYSCLK_SRC_UPLLCK: pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, 1); pll_wait_for_lock(1); pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); break; } /* Update the SystemFrequency variable */ SystemCoreClockUpdate(); #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) /* Signal that the internal frequencies are setup */ sysclk_initialized = 1; #endif }