Example #1
0
/*! \brief Initializes the MCU system clocks.
 */
static void init_sys_clocks(void)
{
    // Switch to OSC0 to speed up the booting
    pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);

    // Start oscillator1
    pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
    //
    pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);

    // Set PLL0 (fed from OSC1 = 11.2896 MHz) to 112.896 MHz
    // We use OSC1 since we need a correct master clock for the SSC module to generate
    // the correct sample rate
    pm_pll_setup(&AVR32_PM, 0,  // pll.
                 SYS_CLOCK_PLL_MUL-1,   // mul.
                 1,   // div.
                 1,   // osc.
                 16); // lockcount.

    // Set PLL operating range and divider (fpll = fvco/2)
    // -> PLL0 output = 62.0928 MHz
    pm_pll_set_option(&AVR32_PM, 0, // pll.
                      1,  // pll_freq.
                      1,  // pll_div2.
                      0); // pll_wbwdisable.

    // start PLL0 and wait for the lock
    pm_pll_enable(&AVR32_PM, 0);
    pm_wait_for_pll0_locked(&AVR32_PM);
    // Set all peripheral clocks torun at master clock rate
    pm_cksel(&AVR32_PM,
             0,   // pbadiv.
             0,   // pbasel.
             0,   // pbbdiv.
             0,   // pbbsel.
             0,   // hsbdiv.
             0);  // hsbsel.

    // Set one waitstate for the flash
    flashc_set_wait_state(1);

    // Switch to PLL0 as the master clock
    pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);

#if (defined USB_RESYNC_METHOD) && (USB_RESYNC_METHOD == USB_RESYNC_METHOD_EXT_CLOCK_SYNTHESIZER)
    // Holds frequencies parameters
    g_fcpu_hz = g_fhsb_hz = g_fpba_hz = g_fpbb_hz = FMCK_HZ(11289600);
#endif

#if (defined __GNUC__) && (defined __AVR32__)
    // Give the used PBA clock frequency to Newlib, so it can work properly.
    set_cpu_hz(FPBA_HZ);
#endif
    init_usb_clock();
    init_codec_gclk();
}
Example #2
0
File: demo.c Project: kerichsen/asf
/*! \brief Initializes the MCU system clocks.
 */
void init_sys_clocks(void)
{
  // Switch to OSC0 to speed up the booting
  pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);

  // Start oscillator1
  pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
  pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);

  // Set PLL0 (fed from OSC0 = 12 MHz) to 132 MHz
  // We use OSC1 since we need a correct master clock for the SSC module to generate
  // the correct sample rate
  pm_pll_setup(&AVR32_PM, 0,  // pll.
    10,  // mul.
    1,   // div.
    0,   // osc.
    16); // lockcount.

  // Set PLL operating range and divider (fpll = fvco/2)
  // -> PLL0 output = 66 MHz
  pm_pll_set_option(&AVR32_PM, 0, // pll.
    1,  // pll_freq.
    1,  // pll_div2.
    0); // pll_wbwdisable.

  // start PLL0 and wait for the lock
  pm_pll_enable(&AVR32_PM, 0);
  pm_wait_for_pll0_locked(&AVR32_PM);
  // Set all peripheral clocks torun at master clock rate

  // Set one waitstate for the flash
  flashc_set_wait_state(1);

  // Switch to PLL0 as the master clock
  pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);

  // Use 12MHz from OSC0 and generate 96 MHz
  pm_pll_setup(&AVR32_PM, 1,  // pll.
	  7,   // mul.
	  1,   // div.
	  0,   // osc.
	  16); // lockcount.

  pm_pll_set_option(&AVR32_PM, 1, // pll.
	  1,  // pll_freq: choose the range 80-180MHz.
	  1,  // pll_div2.
	  0); // pll_wbwdisable.

  // start PLL1 and wait forl lock
  pm_pll_enable(&AVR32_PM, 1);

  // Wait for PLL1 locked.
  pm_wait_for_pll1_locked(&AVR32_PM);

}
/*! \brief Initializes the MCU system clocks.
 */
void init_sys_clocks(void)
{
  // Switch to OSC0 to speed up the booting
  pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);

  // Start oscillator1
  pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
  //
  pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);

  // Set PLL0 (fed from OSC1 = 11.2896 MHz) to 124.1856 MHz
  // We use OSC1 since we need a correct master clock for the SSC module to generate
  // the correct sample rate
  pm_pll_setup(&AVR32_PM, 0,  // pll.
    10,  // mul.
    1,   // div.
    1,   // osc.
    16); // lockcount.

  // Set PLL operating range and divider (fpll = fvco/2)
  // -> PLL0 output = 62.0928 MHz
  pm_pll_set_option(&AVR32_PM, 0, // pll.
    1,  // pll_freq.
    1,  // pll_div2.
    0); // pll_wbwdisable.

  // start PLL0 and wait for the lock
  pm_pll_enable(&AVR32_PM, 0);
  pm_wait_for_pll0_locked(&AVR32_PM);
  // Set all peripheral clocks to run at master clock rate
  pm_cksel(&AVR32_PM,
    0,   // pbadiv.
    0,   // pbasel.
    0,   // pbbdiv.
    0,   // pbbsel.
    0,   // hsbdiv.
    0);  // hsbsel.

  // Set one waitstate for the flash
  flashc_set_wait_state(1);

  // Switch to PLL0 as the master clock
  pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);

  init_usb_clock();
  init_codec_gclk();
}
void systemInit(void)
{
   //Low-level initialization
   _init_startup();

   //Switch main clock to OSC0 (12MHz)
   pm_switch_to_osc0(&AVR32_PM, OSC0_FREQ, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);

   //Start OSC1 (11.2896MHz)
   pm_enable_osc1_crystal(&AVR32_PM, OSC1_FREQ);
   pm_enable_clk1(&AVR32_PM, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);

   //Configure PLL0 (132MHz)
   pm_pll_setup(&AVR32_PM, 0, 10, 1, 0, 16);
   //Set PLL operating range (80 to 180MHz) and output divider (2)
   pm_pll_set_option(&AVR32_PM, 0, 1, 1, 0);

   //Start PLL0
   pm_pll_enable(&AVR32_PM, 0);
   //Wait for the PLL to lock
   pm_wait_for_pll0_locked(&AVR32_PM);

   //Set FLASH wait-state
   flashc_set_wait_state(1);

   //Switch main clock to PLL0
   pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);

   //Configure PLL1 (96MHz)
   pm_pll_setup(&AVR32_PM, 1, 7, 1, 0, 16);
   //Set PLL operating range (80 to 180MHz) and output divider (2)
   pm_pll_set_option(&AVR32_PM, 1, 1, 1, 0);

   //Start PLL1
   pm_pll_enable(&AVR32_PM, 1);
   //Wait for the PLL to lock
   pm_wait_for_pll1_locked(&AVR32_PM);

   //Set clock dividers for PBA, PBB and HSB clocks
   pm_cksel(&AVR32_PM, 0, 0, 0, 0, 0, 0);

   //Initialize SDRAM memory
   sdramc_init(HSB_FREQ);
}
Example #5
0
/**
 * Initializes the MCU system clocks.
 */
static void
init_sys_clocks(void)
{

        /* if we don't run on OSC0 don't switch to it since we don't know
         * what kind of oscillator we have here
         */
          
#if OSC == 0
        /* switch to OSC0 to speed up the booting */
        pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
#endif

        
#ifndef USE_PLL
        return;
#endif
        
        /* For audio, ee have to use OSC1 on to generate the correct clockrate
         * for the SSC
         */
#if OSC == 1
        /* start oscillator1 */
        pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
        pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
#endif

        /* configure pll multipliers */
        pm_pll_setup(&AVR32_PM,
                     0,          /* pll */
                     PLL_MUL,    /* mul */
                     1,          /* div */
                     OSC,        /* osc */
                     16);        /* lockcount */

        /* set PLL operating range and divider (fpll = fvco/2)
         * this gives PLL output = 66 MHz (62.0928 MHz for EVK1105/OSC1)
         */
        pm_pll_set_option(&AVR32_PM,
                          0,  /* pll */
                          1,  /* pll_freq */
                          1,  /* pll_div2 */
                          0); /* pll_wbwdisable. */
  

        /* start PLL0 and wait for the lock */
        pm_pll_enable(&AVR32_PM, 0);
        pm_wait_for_pll0_locked(&AVR32_PM);
        
        /* Set all peripheral clocks torun at master clock rate */
        pm_cksel(&AVR32_PM,
                 0,   /* pbadiv */
                 0,   /* pbasel */
                 0,   /* pbbdiv */
                 0,   /* pbbsel */
                 0,   /* hsbdiv */
                 0);  /* hsbsel */ 
        
        /* Set one waitstate for the flash */
        flashc_set_wait_state(1);
        
        /* Switch to PLL0 as the master clock */
        pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
}
Example #6
0
//!
//! @brief This function initializes the hardware/software resources
//! required for device CDC task.
//!
void AK5394A_task_init(void)
{
	// Set up CS4344
	// Set up GLCK1 to provide master clock for CS4344
	gpio_enable_module_pin(GCLK1, GCLK1_FUNCTION);	// for DA_SCLK
													// LRCK is SCLK / 64 generated by TX_SSC
													// so SCLK of 6.144Mhz ===> 96khz

	pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
					  0,                  // osc_or_pll: use Osc (if 0) or PLL (if 1)
					  1,                  // pll_osc: select Osc0/PLL0 or Osc1/PLL1
					  1,                  // diven - enabled
					  0);                 // divided by 2.  Therefore GCLK1 = 6.144Mhz
	pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);

	pm_enable_osc1_ext_clock(&AVR32_PM);	// OSC1 is clocked by 12.288Mhz Osc
												// from AK5394A Xtal Oscillator
	pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);

	// Set up AK5394A
	gpio_clr_gpio_pin(AK5394_RSTN);		// put AK5394A in reset
	gpio_clr_gpio_pin(AK5394_DFS0);		// L L  -> 48khz
	gpio_clr_gpio_pin(AK5394_DFS1);
	gpio_set_gpio_pin(AK5394_HPFE);		// enable HP filter
	gpio_clr_gpio_pin(AK5394_ZCAL);		// use VCOML and VCOMR to cal
	gpio_set_gpio_pin(AK5394_SMODE1);	// SMODE1 = H for Master i2s
	gpio_set_gpio_pin(AK5394_SMODE2);	// SMODE2 = H for Master/Slave i2s

    gpio_set_gpio_pin(AK5394_RSTN);		// start AK5394A
    while (gpio_get_pin_value(AK5394_CAL)); // wait till CAL goes low

		// Assign GPIO to SSC.
	  gpio_enable_module(SSC_GPIO_MAP, sizeof(SSC_GPIO_MAP) / sizeof(SSC_GPIO_MAP[0]));
	  gpio_enable_pin_glitch_filter(SSC_RX_CLOCK);
	  gpio_enable_pin_glitch_filter(SSC_RX_DATA);
	  gpio_enable_pin_glitch_filter(SSC_RX_FRAME_SYNC);
	  gpio_enable_pin_glitch_filter(SSC_TX_CLOCK);
	  gpio_enable_pin_glitch_filter(SSC_TX_DATA);
	  gpio_enable_pin_glitch_filter(SSC_TX_FRAME_SYNC);

	  current_freq.frequency = 96000;

	  // set up SSC
	  ssc_i2s_init(ssc, 96000, 24, 32, SSC_I2S_MODE_STEREO_OUT_STEREO_IN, FPBA_HZ);

	  // set up PDCA
	  // In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix
	  // provides specific logic in order to re-arbitrate before the end of the INCR transfer.
	  //
	  // HSB Bus Matrix: By default the HSB bus matrix mode is in Undefined length burst type (INCR).
	  // Here we have to put in single access (the undefined length burst is treated as a succession of single
	  // accesses, allowing re-arbitration at each beat of the INCR burst.
	  // Refer to the HSB bus matrix section of the datasheet for more details.
	  //
	  // HSB Bus matrix register MCFG1 is associated with the CPU instruction master interface.
	  AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_CPU_INSN] = 0x1;

	  audio_buffer_in = 0;
	  spk_buffer_out = 0;
	  // Register PDCA IRQ interrupt.
	  pdca_set_irq();

	  // Init PDCA channel with the pdca_options.
	  pdca_init_channel(PDCA_CHANNEL_SSC_RX, &PDCA_OPTIONS); // init PDCA channel with options.
      pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
      pdca_init_channel(PDCA_CHANNEL_SSC_TX, &SPK_PDCA_OPTIONS); // init PDCA channel with options.
       pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_TX);

       //////////////////////////////////////////////
       // Enable now the transfer.
       pdca_enable(PDCA_CHANNEL_SSC_TX);


	  xTaskCreate(AK5394A_task,
              configTSK_AK5394A_NAME,
              configTSK_AK5394A_STACK_SIZE,
              NULL,
              configTSK_AK5394A_PRIORITY,
              NULL);

}
Example #7
0
void board_init(void)
{
	
		// first change to OSC0 (12MHz)
		pm_enable_osc0_crystal(& AVR32_PM, FOSC0);            // Enable the Osc0 in crystal mode
		pm_enable_clk0(& AVR32_PM, OSC0_STARTUP);                  // Crystal startup time
		pm_switch_to_clock(& AVR32_PM, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
		
		
		
		pm_enable_osc1_ext_clock(& AVR32_PM);  // ocs1 is external clock
		pm_enable_clk1(& AVR32_PM, OSC1_STARTUP);
		
		pm_pll_setup(&AVR32_PM
		, 0   // pll
		, 3 // mul
		, 0 // div  ->  f_vfo = 16.384 MHz * 8 = 131.072 MHz
		, 1   // osc
		, 16  // lockcount
		);
		
		pm_pll_set_option(&AVR32_PM
		, 0 // pll
		, 1 // pll_freq  (f_vfo range 80MHz - 180 MHz)
		, 1 // pll_div2  (f_pll1 = f_vfo / 2)
		, 0 // pll_wbwdisable
		);
		
		pm_pll_enable(&AVR32_PM, 0);
		
		pm_wait_for_pll0_locked(&AVR32_PM);
		
		pm_cksel(&AVR32_PM
		, 1, 1 // PBA  (CPU / 4) = 16.384 MHz
		, 0, 0 // PBB  65.536 MHz
		, 0, 0 // HSB	 = CPU 65.536 MHz
		);
		
		flashc_set_wait_state(1);  // one wait state if CPU clock > 33 MHz
		
		pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); // switch to PLL0
		
		
		// --------------------------------------
		
		// USB clock
		
		// Use 12MHz from OSC0 and generate 96 MHz
		pm_pll_setup(&AVR32_PM, 1,  // pll.
		7,   // mul.
		1,   // div.
		0,   // osc.
		16); // lockcount.

		pm_pll_set_option(&AVR32_PM, 1, // pll.
		1,  // pll_freq: choose the range 80-180MHz.
		1,  // pll_div2.
		0); // pll_wbwdisable.

		// start PLL1 and wait forl lock
		pm_pll_enable(&AVR32_PM, 1);

		// Wait for PLL1 locked.
		pm_wait_for_pll1_locked(&AVR32_PM);

		pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,  // gc.
		1,  // osc_or_pll: use Osc (if 0) or PLL (if 1).
		1,  // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
		0,  // diven.
		0); // div.
		pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
		
		// --------------------------------------
	
	// LCD display
	
	gpio_enable_gpio( lcd_gpio_map, sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] ) );
	
	int i;
	
	for (i=0; i < (sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] )); i++)
	{
		gpio_configure_pin( lcd_gpio_map[i].pin, lcd_gpio_map[i].function);
	}
	
	
	gpio_enable_module( lcd_pwm_gpio_map, sizeof( lcd_pwm_gpio_map ) / sizeof( lcd_pwm_gpio_map[0] ) );
	
	
	// Backlight
	AVR32_PWM.channel[6].CMR.cpre = 3;
	AVR32_PWM.channel[6].cprd = 1000;
	AVR32_PWM.channel[6].cdty = 500;
	
	AVR32_PWM.ENA.chid6 = 1;
	
	// contrast
	AVR32_PWM.channel[0].CMR.cpre = 3;
	AVR32_PWM.channel[0].cprd = 1000;
	AVR32_PWM.channel[0].cdty = 520;
	
	AVR32_PWM.ENA.chid0 = 1;
	
	
	

	// switches

	gpio_enable_gpio( switch_gpio_map, sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] ) );
	
	for (i=0; i < (sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] )); i++)
	{
		gpio_configure_pin( switch_gpio_map[i].pin, switch_gpio_map[i].function);
	}
	
	
	// USART
	
	gpio_enable_module( usart_gpio_map, sizeof( usart_gpio_map ) / sizeof( usart_gpio_map[0] ) );
	
	
	
}
/**
 * @brief Start PLL @ 48Mhz to run with
 */
void Start_PLL(void)
{
    volatile avr32_pm_t *pm = &AVR32_PM;

    // Switch the main clock to OSC0
    pm_switch_to_osc0(pm, BOARD_OSC0_HZ, BOARD_OSC0_STARTUP_US);

    // For FOSC0 = 12.288 MHz:
    // Setup PLL0 on OSC0, mul=15 ,no divisor, lockcount=16, ie. 12 MHz x 16 = 196.608 MHz output.
	// Division by 2 (in options) yields PLL0 output as 98.304 MHz.
    // The formula is here:
    // if (PLLDIV > 0)
    //     fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
    // else
    //     fVCO = 2*(PLLMUL+1) • fOSC;
	// Lock count defines the PLL settling time (0x00 .. 0x3F.)
    pm_pll_setup(
        pm,     // volatile avr32_pm_t *pm
        0,      // PLL number(0 for PLL0, 1 for PLL1)
        15,     // PLL MUL in the PLL formula
        1,      // PLL DIV in the PLL formula
        0,      // OSC number (0 for osc0, 1 for osc1)
        16);    // unsigned int lockcount

    // Set PLL options to run @ 96 MHz
    pm_pll_set_option(
        pm,     // volatile avr32_pm_t *pm
        0,      // PLL number(0 for PLL0, 1 for PLL1)
        0,      // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
        1,      // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
        0);     // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
                // out-of-lock time). 0 to enable the Wide-Bandwidth Mode.

    // Enable PLL0 and wait for it to lock.
    pm_pll_enable(pm, 0);
    pm_wait_for_pll0_locked(pm);
#if 0
#if defined(BOARD_OSC1_HZ)
    // We need to enable the crystal by hand. We didn't need to do that for OSC0
	// because the call to pm_switch_to_osc0() contains all that housekeeping.
	// But here we don't want to "switch to" the crystal.
    pm_enable_osc1_crystal(pm, BOARD_OSC1_HZ);      // Enable the OSC1 in crystal mode
    pm_enable_clk1(pm, BOARD_OSC1_STARTUP_US);

    // For FOSC1 = 12.000 MHz:
    // Setup PLL1 on OSC1, mul=15 ,no divisor, ie. 12 MHz x 15 = 180 MHz output.
	// Division by 2 (in options) yields PLL0 output as 96.000 MHz.
	// Lock count defines the PLL settling time (0x00 .. 0x3F.)
    // The formula is here:
    // if (PLLDIV > 0)
    //     fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
    // else
    //     fVCO = 2*(PLLMUL+1) • fOSC;
    pm_pll_setup(
        pm,     // volatile avr32_pm_t *pm
        1,      // PLL number(0 for PLL0, 1 for PLL1)
        15,     // PLL MUL in the PLL formula
        1,      // PLL DIV in the PLL formula
        1,      // OSC number (0 for osc0, 1 for osc1)
        16);    // unsigned int lockcount

    // Set PLL options to run @ 96.000 MHz
    pm_pll_set_option(
        pm,     // volatile avr32_pm_t *pm
        1,      // PLL number(0 for PLL0, 1 for PLL1)
        0,      // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
        1,      // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
        0);     // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
                // out-of-lock time). 0 to enable the Wide-Bandwidth Mode.

    // Enable PLL1 and wait for it to lock.
    pm_pll_enable(pm, 1);
    pm_wait_for_pll1_locked(pm);

#endif /* defined(BOARD_OSC1_HZ) */
#endif
    // Select clocks as follows, considering that we are fed with PLL0 (98.304 MHz)
    // fHSB = fMain/2, or 49.152 MHz
    // fPBA = fMain/8, or 12.288 MHz
    // fPBB = fMain/2, or 49.152 MHz
    // ========================================
    // The formula (applies to all three channels, they are the same.)
    //
    // if (xDIV)  // Is the divisor enabled?
    //     fBUS = fMain / 2^(xSEL+1);   // Yes
    // else
    //     fBUS = fMain;                // No
    pm_cksel(
        pm,     // volatile avr32_pm_t *pm
        true,   // PBADIV: Peripheral Bus A clock divisor enable
        0,      // PBASEL: Peripheral Bus A divisor tap (fPBA = fMain/2, or 49.152 MHz)
        true,   // PBBDIV: Peripheral Bus B clock divisor enable
        0,      // PBBSEL: Peripheral Bus B select (fPBB = fMain/2, or 49.152 MHz)
        1,      // CPUDIV: CPU/HSB clock divisor enable
        0);     // CPUSEL: CPU/HSB clock divisor tap (fHSB = fMain/2, or 49.152 MHz)

    // One wait state at 48 MHz (required at fHSB > 33 MHz)
    flashc_set_wait_state(1);

    // Select the PLL0 as the clock source.
    pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0);
#if 0
#if defined(BOARD_OSC1_HZ)
    // Timers, communication modules, and other modules connected to external circuitry may require
    // specific clock frequencies to operate correctly. The Power Manager contains an implementation
    // defined number of generic clocks that can provide a wide range of accurate clock frequencies.
    // Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
    // can optionally be divided by any even integer up to 512. Each clock can be independently
    // enabled and disabled, and is also automatically disabled along with peripheral clocks by the
    // Sleep Controller.

    // Setup generic clock number 0 on PLL, with OSC0/PLL0, no divisor.
    // A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
    // either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
    // The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
    // resulting in the output frequency:
    //
    // fGCLK = fSRC / (2*(DIV+1))
    //
	// In this particular case we enable the generic clock to the USB module. Since the PLL1 is
	// producing 96.000 MHz we want to divide it by 2 to whittle it down to 48.000 +/- 0.25%.
	// The 48 MHz is the only clock that the USB module can use.
	//
    pm_gc_setup(
        pm,     // volatile avr32_pm_t *pm
        AVR32_PM_GCLK_USBB, // Generic clock number
        1,      // Use Osc (=0) or PLL (=1)
        1,      // Select Osc0/PLL0 or Osc1/PLL1
        1,      // DIVEN: Generic clock divisor enable
        0);     // DIV: Generic clock divisor (divide by 2)

    // Enable Generic clock 4 */
    pm_gc_enable(pm, AVR32_PM_GCLK_USBB);

#endif
#endif
#if 0 // Enable only for debugging, or if you really need to output the generic clock...
    pm_gc_setup(
        pm,     // volatile avr32_pm_t *pm
        AVR32_PM_GCLK_GCLK0, // Generic clock number
        1,      // Use Osc (=0) or PLL (=1)
        0,      // Select Osc0/PLL0 or Osc1/PLL1
        0,      // DIVEN: Generic clock divisor enable
        1);     // DIV: Generic clock divisor (divide by 0)

    // Enable Generic clock 0 */
    pm_gc_enable(pm, AVR32_PM_GCLK_GCLK0);

    /* Output the clock AVR32_PM_GCLK_GCLK0 to a GPIO (PB19) */
    gpio_enable_module_pin(AVR32_PM_GCLK_0_1_PIN, AVR32_PM_GCLK_0_1_FUNCTION);
#endif
}