void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
pmc_init_pll(AT91C_PMC_IPLLA_3);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Initialize timer */
timer_init();
/* Initialize the DBGU */
initialize_dbgu();
#if defined(CONFIG_LPDDR2)
lpddr2_init();
#endif
/* Initialize 1-Wire */
one_wire_hw_init();
/* Reset HDMI SiI9022 */
SiI9022_hw_reset();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator is supposed
* to be enabled PCK = MCK = MOSC
*/
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
/* not needed for SAMA5D4 */
pmc_init_pll(0);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_ENTER_NWD)
cpacr_init();
/* Program the DACR to allow client access to *all* domains */
dacr_swd_init();
#endif
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
#if defined(CONFIG_MATRIX)
matrix_read_slave_security();
matrix_read_periperal_security();
#endif
/* Init timer */
timer_init();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
/* Switch PCK/MCK on Main Clock output */
pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
/* No need: we keep what is set in ROM code */
//pmc_init_pll(0x3);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
/* Init timer */
timer_init();
#if defined(CONFIG_DDR3)
/* Initialize MPDDR Controller */
ddramc_init();
#elif defined(CONFIG_LPDDR1)
lpddr1_init();
#elif defined(CONFIG_LPDDR2)
lpddr2_init();
#elif defined(CONFIG_LPDDR3)
lpddr3_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
at91_init_can_message_ram();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA/2 = 3 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Configure the EBI Slave Slot Cycle to 64 */
writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
(AT91C_BASE_MATRIX + MATRIX_SCFG3));
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_SDRAM
/* Initlialize sdram controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator
* is supposed to be enabled PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
pmc_init_pll(AT91C_PMC_IPLLA_3);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
#ifdef CONFIG_USER_HW_INIT
/* Set GMAC & EMAC pins to output low */
at91_special_pio_output_low();
#endif
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* initialize the dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
#ifdef CONFIG_PM_EXTERNAL_DEVICES
#ifdef CONFIG_MACB
/* Make PHYs to power down mode */
phys_enter_power_down();
#endif /* #ifdef CONFIG_MACB */
#endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR);
/* Initialize matrix */
at91_matrix_hw_init();
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_SDRAM
/* Initlialize sdram controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator is supposed to be enabled PCK = MCK = MOSC */
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA/2 = 3 * MCK */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* initialize the dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* load one wire information */
one_wire_hw_init();
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
HDMI_Qt1070_workaround();
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator
* is supposed to be enabled PCK = MCK = MOSC */
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA/2 = 3 * MCK */
pmc_cfg_mck(BOARD_PRESCALER, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(0x1302, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
/* do some special init */
ek_special_hw_init();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is
* supposed to be enabled PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
/* one wire pin init */
one_wire_hw_init();
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
at91_matrix_hw_init();
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_SDRAM
/* Initialize SDRAMC0 */
sdramc0_init();
#endif
#if defined(CONFIG_PSRAM)
psram_hw_init();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator is
*supposed to be enabled PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA/2 = 3 * MCK */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/*Enable External Reset */
writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
/* one wire pin init */
one_wire_hw_init();
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
/* Switch PCK/MCK clock source to the main clock */
pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch MCK clock source to PLLA */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable external reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
/* Init timer */
timer_init();
#if defined(CONFIG_DDR3)
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator
* is supposed to be enabled PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
/* do some special init */
ek_special_hw_init();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* Adjust waitstates to access internal flash */
writel(AT91C_EEFC_FWS_6WS, AT91C_BASE_EEFC + EEFC_FMR);
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
#ifdef CONFIG_DEBUG
/* Initialize dbgu */
initialize_dbgu();
#endif
#ifdef CONFIG_SDRAM
/* Configure SDRAM Controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator
* is supposed to be enabled PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* Initialize PLLA charge pump */
pmc_init_pll(AT91C_PMC_IPLLA_3);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
#ifdef CONFIG_USER_HW_INIT
/* Set GMAC & EMAC pins to output low */
at91_special_pio_output_low();
#endif
/* Disable the software modem clock */
at91_disable_smd_clock();
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* initialize the dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
#ifdef CONFIG_TWI
twi_init();
#endif
#ifdef CONFIG_ACT8865
/* Set ACT8865 REG power saving mode */
act8865_set_power_saving_mode();
/* Set ACT8865 output voltage */
sama5d4ek_act8865_set_reg_voltage();
/* Dsiable ACT8865 I2C interface */
if (act8865_workaround_disable_i2c())
while (1)
;
#endif
#ifdef CONFIG_PM_EXTERNAL_DEVICES
#ifdef CONFIG_MACB
/* Make PHYs to power down mode */
phys_enter_power_down();
#endif
#endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Configure PLLB
*/
pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure the PIO controller
*/
pio_setup(hw_pio);
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
(AT91C_BASE_MATRIX + MATRIX_SCFG3));
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_DEBUG */
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix (memory voltage = 3.3)
*/
writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC |
(1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif /* CONFIG_SDRAM */
}
/*------------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLL_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLL = 2 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller to output PCK0
*/
pio_setup(hw_pio);
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_VERBOSE */
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_MATRIX_SCFG4)) & ~0xFF) | 0x40, AT91C_MATRIX_SCFG4);
/*
* Initialize the matrix Slave 0 & Slave 4 (SRAM & EBI)
*/
writel(readl(AT91C_MATRIX_SCFG0) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG0);
writel(readl(AT91C_MATRIX_SCFG4) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG4);
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix
*/
writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_CCFG_EBICSA);
#ifdef MCK_100
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#else /* 133 MHz */
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator is supposed
* to be enabled PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* Initialize PLLA charge pump */
/* not needed for SAMA5D4 */
pmc_init_pll(0);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/* Setup AHB 32-bit Matrix Divisor */
pmc_cfg_h32mxdiv(BOARD_H32MX, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_ENTER_NWD)
cpacr_init();
/* Program the DACR to allow client access to *all* domains */
dacr_swd_init();
#endif
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
/* Redirect all interrupts to non-secure AIC */
redirect_interrupts_to_aic();
#if defined(CONFIG_MATRIX)
matrix_read_slave_security();
matrix_read_periperal_security();
#endif
/* Init timer */
timer_init();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* load one wire information */
one_wire_hw_init();
/* Reset HDMI SiI9022 */
SiI9022_hw_reset();
/* Disable software modem device's clock */
at91_disable_smd_clock();
#ifdef CONFIG_TWI
twi_init();
#endif
#ifdef CONFIG_ACT8865
/* Set ACT8865 REG power saving mode */
act8865_set_power_saving_mode();
/* Set ACT8865 output voltage */
sama5d4ek_act8865_set_reg_voltage();
/* Dsiable ACT8865 I2C interface */
if (act8865_workaround_disable_i2c())
while (1)
;
#endif
#ifdef CONFIG_PM_EXTERNAL_DEVICES
#ifdef CONFIG_HDMI
SiI9022_enter_power_state_D3_Cold();
#endif
#ifdef CONFIG_WM8904
wm8904_enter_low_power();
#endif
#ifdef CONFIG_MACB
/* Make PHYs to power down mode */
phys_enter_power_down();
#endif
#endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(hw_pio);
/*
* Enable Debug messages on the DBGU
*/
#ifdef CONFIG_DEBUG
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif
#ifdef CONFIG_DDR2
/*
* Configure DDRAM Controller
*/
dbg_log(1, "Init DDR... ");
ddramc_hw_init();
dbg_log(1, "Done!\n\r");
#endif /* CONFIG_DDR2 */
}
