// [main_tc_configure]
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC */
pmc_enable_periph_clk(ID_TC0);
#if SAMG55
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_3);
pmc_switch_pck_to_sclk(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_3);
#endif
/** Configure TC for a 4Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(4, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#ifdef LED1_GPIO
/** Start the counter if LED1 is enabled. */
if (g_b_led1_active) {
tc_start(TC0, 0);
}
#else
tc_start(TC0, 0);
#endif
}
/**
* \brief Initial the codec for audio play.
*/
static void init_dac(void)
{
uint32_t ul_value;
/* First, disable programmable clock */
pmc_disable_pck(PMC_PCK_0);
/* Then, configure PMC Programmable Clock */
pmc_switch_pck_to_mainck(PMC_PCK_0, PMC_MCKR_PRES_CLK_1);
/* Finally, enable programmable clock */
pmc_enable_pck(PMC_PCK_0);
/* init control interface */
init_twi_wm8731();
/* reset the WM8731 */
wm8731_reset();
/* Select the WM8731 DAC */
wm8731_dac_select(1);
/* Set the WM8731 to usb mode and 48K DAC */
wm8731_set_sampling_control(1,0,0);
/* Set the WM8731 audio interface to I2S mode */
ul_value = WM8731_REG_DIGITAL_AUDIO_INTERFACE_FORMAT_I2S;
wm8731_set_digital_audio_data_bit_length(ul_value);
/* Set the WM8731 audio data bit length to 16bit */
ul_value = WM8731_REG_DIGITAL_AUDIO_INTERFACE_FORMAT_IWL_16_BIT;
wm8731_set_digital_audio_data_bit_length(ul_value);
/* Disable the WM8731 DAC soft mute */
wm8731_set_dac_soft_mute(0);
/* Power up the WM8731 DAC */
wm8731_power_mode_dac();
/* Active the WM8731 */
wm8731_set_active(1);
}
/**
* \brief Configure UART with the given master clock, and Configure PCK with
* the given divider source of master clock and prescaler.
*
* \param ul_clock_source The master clock divider source.
* \param ul_prescaler Master Clock prescaler.
* \param ul_master_clock Frequency of the master clock (in Hz).
*/
static void config_uart_and_pck(uint32_t ul_clock_source,
uint32_t ul_prescaler, uint32_t ul_master_clock)
{
if (ul_master_clock > BOARD_FREQ_SLCK_XTAL) {
const sam_uart_opt_t uart_console_settings = {
ul_master_clock, PMC_CLOCK_SWITCHING_EXAMPLE_BAUDRATE,
UART_MR_PAR_NO
};
/* Configure PMC */
pmc_enable_periph_clk(CONSOLE_UART_ID);
/* Configure UART */
uart_init(CONSOLE_UART, &uart_console_settings);
}
/* Programmable clock output disabled */
pmc_disable_pck(GCLK_ID);
/* Configure PMC Programmable Clock */
switch (ul_clock_source) {
case PMC_PCK_CSS_MAIN_CLK:
pmc_switch_pck_to_mainck(GCLK_ID, ul_prescaler);
break;
case PMC_PCK_CSS_SLOW_CLK:
pmc_switch_pck_to_sclk(GCLK_ID, ul_prescaler);
break;
case PMC_PCK_CSS_PLLA_CLK:
pmc_switch_pck_to_pllack(GCLK_ID, ul_prescaler);
break;
#if (SAM3S || SAM4S || SAM4C)
case PMC_PCK_CSS_PLLB_CLK:
pmc_switch_pck_to_pllbck(GCLK_ID, ul_prescaler);
break;
#endif
default:
pmc_switch_pck_to_mainck(GCLK_ID, ul_prescaler);
}
/* Enable the PCK again */
pmc_enable_pck(GCLK_ID);
}
/**
* \brief Enable the FLEXCOM module.
*
* \param p_flexcom Pointer to a FLEXCOM instance.
*
*/
void flexcom_enable(Flexcom *p_flexcom)
{
sleepmgr_lock_mode(SLEEPMGR_ACTIVE);
/* Enable PMC clock for FLEXCOM */
#ifdef ID_USART7
if (p_flexcom == FLEXCOM7) {
sysclk_enable_peripheral_clock(ID_USART7);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_7);
pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_7);
} else
#endif
#ifdef ID_USART6
if (p_flexcom == FLEXCOM6) {
sysclk_enable_peripheral_clock(ID_USART6);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_7);
pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_7);
} else
#endif
#ifdef ID_USART5
if (p_flexcom == FLEXCOM5) {
sysclk_enable_peripheral_clock(ID_USART5);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_7);
pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_7);
} else
#endif
#ifdef ID_USART4
if (p_flexcom == FLEXCOM4) {
sysclk_enable_peripheral_clock(ID_USART4);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_7);
pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_7);
} else
#endif
#ifdef ID_USART3
if (p_flexcom == FLEXCOM3) {
sysclk_enable_peripheral_clock(ID_USART3);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_6);
pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_6);
} else
#endif
#ifdef ID_USART2
if (p_flexcom == FLEXCOM2) {
sysclk_enable_peripheral_clock(ID_USART2);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_6);
pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_6);
} else
#endif
#ifdef ID_USART1
if (p_flexcom == FLEXCOM1) {
sysclk_enable_peripheral_clock(ID_USART1);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_6);
pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_6);
} else
#endif
#ifdef ID_USART0
if (p_flexcom == FLEXCOM0) {
sysclk_enable_peripheral_clock(ID_USART0);
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_6);
pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_6);
} else
#endif
{
Assert(false);
}
}
