C++ (Cpp) pmc_start_ctrs Examples

Example #1

File: op_model_fsl_booke.c Project: 3sOx/asuswrt-merlin

static void fsl_booke_start(struct op_counter_config *ctr)
{
	int i;

	mtmsr(mfmsr() | MSR_PMM);

	for (i = 0; i < num_counters; ++i) {
		if (ctr[i].enabled) {
			ctr_write(i, reset_value[i]);
			/* Set each enabled counter to only
			 * count when the Mark bit is *not* set */
			set_pmc_marked(i, 1, 0);
			pmc_start_ctr(i, 1);
		} else {
			ctr_write(i, 0);

			/* Set the ctr to be stopped */
			pmc_start_ctr(i, 0);
		}
	}

	/* Clear the freeze bit, and enable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PMM bit */
	pmc_start_ctrs(1);

	oprofile_running = 1;

	pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
			mfpmr(PMRN_PMGC0));
}

Example #2

File: op_model_fsl_emb.c Project: 274914765/C

static void fsl_emb_handle_interrupt(struct pt_regs *regs,
                    struct op_counter_config *ctr)
{
    unsigned long pc;
    int is_kernel;
    int val;
    int i;

    /* set the PMM bit (see comment below) */
    mtmsr(mfmsr() | MSR_PMM);

    pc = regs->nip;
    is_kernel = is_kernel_addr(pc);

    for (i = 0; i < num_counters; ++i) {
        val = ctr_read(i);
        if (val < 0) {
            if (oprofile_running && ctr[i].enabled) {
                oprofile_add_ext_sample(pc, regs, i, is_kernel);
                ctr_write(i, reset_value[i]);
            } else {
                ctr_write(i, 0);
            }
        }
    }

    /* The freeze bit was set by the interrupt. */
    /* Clear the freeze bit, and reenable the interrupt.
     * The counters won't actually start until the rfi clears
     * the PMM bit */
    pmc_start_ctrs(1);
}

Example #3

File: op_model_7450.c Project: romanbb/android_kernel_lge_d851

static void fsl7450_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;

	/*                                     */
	mtmsr(mfmsr() | MSR_PMM);

	pc = mfspr(SPRN_SIAR);
	is_kernel = is_kernel_addr(pc);

	for (i = 0; i < num_pmcs; ++i) {
		val = classic_ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_ext_sample(pc, regs, i, is_kernel);
				classic_ctr_write(i, reset_value[i]);
			} else {
				classic_ctr_write(i, 0);
			}
		}
	}

	/*                                          */
	/*                                                  
                                                          
                 */
	pmc_start_ctrs();
}

Example #4

File: op_model_fsl_emb.c Project: 007kumarraja/rockchip-rk3188-mk908

static void fsl_emb_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;

	pc = regs->nip;
	is_kernel = is_kernel_addr(pc);

	for (i = 0; i < num_counters; ++i) {
		val = ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_ext_sample(pc, regs, i, is_kernel);
				ctr_write(i, reset_value[i]);
			} else {
				ctr_write(i, 0);
			}
		}
	}

	/* The freeze bit was set by the interrupt. */
	/* Clear the freeze bit, and reenable the interrupt.  The
	 * counters won't actually start until the rfi clears the PMM
	 * bit.  The PMM bit should not be set until after the interrupt
	 * is cleared to avoid it getting lost in some hypervisor
	 * environments.
	 */
	mtmsr(mfmsr() | MSR_PMM);
	pmc_start_ctrs(1);
}

Example #5

File: op_model_7450.c Project: mrtos/Logitech-Revue

/* Sets the counters on this CPU to the chosen values, and starts them */
static void fsl7450_start(struct op_counter_config *ctr)
{
	int i;

	mtmsr(mfmsr() | MSR_PMM);

	for (i = 0; i < NUM_CTRS; ++i) {
		if (ctr[i].enabled)
			ctr_write(i, reset_value[i]);
		else
			ctr_write(i, 0);
	}

	/* Clear the freeze bit, and enable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PMM bit */
	pmc_start_ctrs();

	oprofile_running = 1;
}

Example #6

File: op_model_7450.c Project: romanbb/android_kernel_lge_d851

static int fsl7450_start(struct op_counter_config *ctr)
{
	int i;

	mtmsr(mfmsr() | MSR_PMM);

	for (i = 0; i < num_pmcs; ++i) {
		if (ctr[i].enabled)
			classic_ctr_write(i, reset_value[i]);
		else
			classic_ctr_write(i, 0);
	}

	/*                                                
                                                          
                */
	pmc_start_ctrs();

	oprofile_running = 1;

	return 0;
}