int get_hw_ocv(void)
{
#if defined(CONFIG_POWER_EXT)
return 4001;
#else
kal_int32 adc_result_reg=0;
kal_int32 adc_result=0;
kal_int32 r_val_temp=4;
#if defined(SWCHR_POWER_PATH)
adc_result_reg = pmic_get_register_value(PMIC_RG_ADC_OUT_WAKEUP_SWCHR);
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (swchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#else
adc_result_reg = pmic_get_register_value(PMIC_RG_ADC_OUT_WAKEUP_PCHR);
adc_result = (adc_result_reg*r_val_temp*VOLTAGE_FULL_RANGE)/ADC_PRECISE;
bm_print(BM_LOG_CRTI, "[oam] get_hw_ocv (pchr) : adc_result_reg=%d, adc_result=%d\n",
adc_result_reg, adc_result);
#endif
adc_result += g_hw_ocv_tune_value;
return adc_result;
#endif
}
static void spm_sodi_pre_process(void)
{
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
vsram_vosel_on_lb = pmic_get_register_value(PMIC_VSRAM_VOSEL_ON_LB);
spm_write(SPM_PCM_RESERVE3,(pmic_get_register_value(PMIC_VSRAM_VOSEL_OFFSET)<<8)|pmic_get_register_value(PMIC_VSRAM_VOSEL_DELTA));//delta = 0v
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,(vsram_vosel_on_lb&0xff80)|0x28);//0.85v
}
static kal_uint32 charging_get_hv_status(void *data)
{
kal_uint32 status = STATUS_OK;
*(kal_bool*)(data) = pmic_get_register_value(PMIC_RGS_VCDT_HV_DET);
return status;
}
static void spm_dpidle_pre_process(void)
{
/* //TODO
spm_i2c_control(I2C_CHANNEL, 1);//D1,D2 no ext bulk
g_bus_ctrl=spm_read(0xF0001070);
spm_write(0xF0001070 , g_bus_ctrl | (1 << 21)); //bus dcm disable
g_sys_ck_sel = spm_read(0xF0001108);
//spm_write(0xF0001108 , g_sys_ck_sel &~ (1<<1) );
spm_write(0xF0001108 , 0x0);
spm_write(0xF0000204 , spm_read(0xF0000204) | (1 << 0)); // BUS 26MHz enable
*/
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
vsram_vosel_on_lb = pmic_get_register_value(PMIC_VSRAM_VOSEL_ON_LB);
spm_write(SPM_PCM_RESERVE3,(pmic_get_register_value(PMIC_VSRAM_VOSEL_OFFSET)<<8)|pmic_get_register_value(PMIC_VSRAM_VOSEL_DELTA));//delta = 0v
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,(vsram_vosel_on_lb&0xff80)|0x28);//0.85v
}
static kal_uint32 charging_get_battery_status(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 val = 0;
#if defined(CONFIG_POWER_EXT) || defined(CONFIG_MTK_FPGA)
*(kal_bool*)(data) = 0; // battery exist
battery_log(BAT_LOG_CRTI,"bat exist for evb\n");
#else
val=pmic_get_register_value(PMIC_BATON_TDET_EN);
battery_log(BAT_LOG_FULL,"[charging_get_battery_status] BATON_TDET_EN = %d\n", val);
if (val) {
pmic_set_register_value(PMIC_BATON_TDET_EN,1);
pmic_set_register_value(PMIC_RG_BATON_EN,1);
*(kal_bool*)(data) = pmic_get_register_value(PMIC_RGS_BATON_UNDET);
} else {
*(kal_bool*)(data) = KAL_FALSE;
}
#endif
return status;
}
static kal_uint32 charging_get_current(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 array_size;
kal_uint32 reg_value;
array_size = GETARRAYNUM(CS_VTH);
reg_value=pmic_get_register_value(PMIC_RG_CS_VTH);//RG_CS_VTH
*(kal_uint32 *)data = charging_value_to_parameter(CS_VTH,array_size,reg_value);
return status;
}
static kal_uint32 charging_get_charger_det_status(void *data)
{
kal_uint32 status = STATUS_OK;
#if defined(CONFIG_MTK_FPGA)
*(kal_bool*)(data) = 1;
battery_log(BAT_LOG_CRTI,"chr exist for fpga\n");
#else
*(kal_bool*)(data) = pmic_get_register_value(PMIC_RGS_CHRDET);
#endif
return status;
}
void trigger_hw_ocv(void)
{
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SEL,0x1);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x0);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x1);
while(pmic_get_register_value(PMIC_RG_ADC_RDY_WAKEUP_PCHR)==0)
{
bm_print(BM_LOG_FULL, "[trigger_hw_ocv] delay\n");
udelay(100);
}
}
static kal_uint32 charging_set_ta_current_pattern(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 increase = *(kal_uint32*)(data);
kal_uint32 debug_val = 0;
U8 count = 0;
pmic_set_register_value(PMIC_RG_CS_VTH,0xc);
if(increase == KAL_TRUE) {
/* Set communication mode high/low current */
pmic_set_register_value(PMIC_RG_CM_CS_VTHH,0xa);/* 650mA */
pmic_set_register_value(PMIC_RG_CM_CS_VTHL,0xf);/* 70mA */
/* Set CM_VINC high period time (HPRD1, HPRD2) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD1,9);/* 100ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD2,9);/* 100ms */
/* Set CM_VINC high period time (HPRD3, HPRD4) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD3,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD4,29);/* 300ms */
/* Set CM_VINC high period time (HPRD5, HPRD6) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD5,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD6,49);/* 500ms */
/* Enable CM_VINC interrupt */
//mt6325_upmu_set_rg_int_en_pchr_cm_vinc(0x1);
pmic_set_register_value(PMIC_RG_INT_EN_PCHR_CM_VINC,1);
/* Select PCHR debug flag to monitor abnormal abort */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_SEL,0x2e);
/* Enable PCHR debug flag */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_EN,0x1);
/* Trigger CM VINC mode */
pmic_set_register_value(PMIC_RG_CM_VINC_TRIG,0x1);
/* wait for interrupt */
while(pmic_get_register_value(PMIC_PCHR_CM_VINC_STATUS) != 1) {
msleep(50);
count++;
if (count > 42)
break;
}
} else {
/* Set communication mode high/low current */
pmic_set_register_value(PMIC_RG_CM_CS_VTHH,0xa);/* 650mA */
pmic_set_register_value(PMIC_RG_CM_CS_VTHL,0xf);/* 70mA */
/* Set CM_VINC high period time (HPRD1, HPRD2) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD1,29);/* 100ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD2,29);/* 100ms */
/* Set CM_VINC high period time (HPRD3, HPRD4) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD3,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD4,9);/* 300ms */
/* Set CM_VINC high period time (HPRD5, HPRD6) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD5,9);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD6,49);/* 500ms */
/* Enable CM_VINC interrupt */
//mt6325_upmu_set_rg_int_en_pchr_cm_vinc(0x1);
pmic_set_register_value(PMIC_RG_INT_EN_PCHR_CM_VDEC,1);
/* Select PCHR debug flag to monitor abnormal abort */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_SEL,0x2e);
/* Enable PCHR debug flag */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_EN,0x1);
/* Trigger CM VINC mode */
pmic_set_register_value(PMIC_RG_CM_VDEC_TRIG,0x1);
/* wait for interrupt */
while(pmic_get_register_value(PMIC_PCHR_CM_VDEC_STATUS) != 1) {
msleep(50);
count++;
if (count > 42)
break;
}
}
debug_val = pmic_get_register_value(PMIC_RGS_PCHR_FLAG_OUT);
battery_log(BAT_LOG_CRTI, "[charging_set_ta_current_pattern] debug_val=0x%x cnt=%d\n", debug_val,count);
if (count > 10 || debug_val != 0) {
status = STATUS_FAIL;
}
return status;
}
