static int atomisp_resume(struct device *dev)
{
struct atomisp_device *isp = (struct atomisp_device *)
dev_get_drvdata(dev);
int ret;
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2) {
ret = pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_UP,
MRFLD_ISPSSPM0);
if (ret)
return ret;
}
pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
/*Turn on ISP d-phy */
ret = atomisp_ospm_dphy_up(isp);
if (ret) {
v4l2_err(&atomisp_dev,
"Failed to power up ISP!.\n");
return -EINVAL;
}
/*restore register values for iUnit and iUnitPHY registers*/
if (isp->saved_regs.pcicmdsts)
atomisp_restore_iunit_reg(isp);
if (IS_ISP2400)
atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW);
return 0;
}
bool ps_hdmi_power_islands_on()
{
/*
* If pmu_nc_set_power_state fails then accessing HW
* reg would result in a crash - IERR/Fabric error.
*/
if (pmu_nc_set_power_state(OSPM_DISPLAY_B_ISLAND,
OSPM_ISLAND_UP, OSPM_REG_TYPE))
BUG();
return true;
}
static void atomisp_pci_shutdown(struct pci_dev *dev)
{
struct atomisp_device *isp = (struct atomisp_device *)
pci_get_drvdata(dev);
if (IS_ISP2400 && atomisp_mrfld_pre_power_down(isp))
return;
/*Turn off the ISP d-phy*/
if (atomisp_ospm_dphy_down(isp))
return;
pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_DOWN,
MRFLD_ISPSSPM0);
};
static int atomisp_suspend(struct device *dev)
{
struct atomisp_device *isp = (struct atomisp_device *)
dev_get_drvdata(dev);
unsigned long flags;
int ret;
/* FIXME: currently only use subdev[0] in single stream mode */
struct atomisp_sub_device *isp_subdev = &isp->isp_subdev[0];
/*
* FIXME: Suspend is not supported by sensors. Abort if any video
* node was opened.
*/
if (atomisp_dev_users(isp))
return -EBUSY;
spin_lock_irqsave(&isp->lock, flags);
if (isp_subdev->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
spin_unlock_irqrestore(&isp->lock, flags);
v4l2_err(&atomisp_dev,
"atomisp cannot suspend at this time.\n");
return -EINVAL;
}
spin_unlock_irqrestore(&isp->lock, flags);
/* Prepare for MRFLD IUNIT power down */
if (IS_ISP2400) {
ret = atomisp_mrfld_pre_power_down(isp);
if (ret)
return ret;
}
/*Turn off the ISP d-phy */
ret = atomisp_ospm_dphy_down(isp);
if (ret) {
dev_err(isp->dev, "fail to power off ISP\n");
return ret;
}
pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
ret = pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_DOWN,
MRFLD_ISPSSPM0);
return ret;
}
static int atomisp_runtime_suspend(struct device *dev)
{
struct atomisp_device *isp = (struct atomisp_device *)
dev_get_drvdata(dev);
int ret;
if (IS_ISP2400) {
ret = atomisp_mrfld_pre_power_down(isp);
if (ret)
return ret;
}
/*Turn off the ISP d-phy*/
ret = atomisp_ospm_dphy_down(isp);
if (ret)
return ret;
pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
ret = pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_DOWN,
MRFLD_ISPSSPM0);
return ret;
}
/**
* Power on sequence for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dpi_panel_power_on(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs)
{
u32 val = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int retry, reset_count = 10;
int i;
int err = 0;
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
OSPM_UHB_FORCE_POWER_ON))
return -EAGAIN;
reset_recovery:
--reset_count;
/*HW-Reset*/
if (p_funcs && p_funcs->reset)
p_funcs->reset(dsi_config);
/*Enable DSI PLL*/
if (!(REG_READ(regs->dpll_reg) & BIT31)) {
if(ctx->pll_bypass_mode) {
uint32_t dpll = 0;
REG_WRITE(regs->dpll_reg, dpll);
if (ctx->cck_div) {
dpll = dpll | BIT11;
REG_WRITE(regs->dpll_reg, dpll);
udelay(1);
}
dpll = dpll | BIT12;
REG_WRITE(regs->dpll_reg, dpll);
mdelay(1);
dpll = dpll | BIT13;
REG_WRITE(regs->dpll_reg, dpll);
mdelay(1);
} else {
REG_WRITE(regs->dpll_reg, 0x0);
REG_WRITE(regs->fp_reg, 0x0);
REG_WRITE(regs->fp_reg, ctx->fp);
REG_WRITE(regs->dpll_reg, ((ctx->dpll) & ~BIT30));
udelay(2);
val = REG_READ(regs->dpll_reg);
REG_WRITE(regs->dpll_reg, (val | BIT31));
/*wait for PLL lock on pipe*/
retry = 10000;
while (--retry && !(REG_READ(PIPEACONF) & BIT29))
udelay(3);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
}
REG_WRITE(regs->eot_disable_reg,
(REG_READ(regs->eot_disable_reg) & ~BIT1));
REG_WRITE(regs->device_ready_reg, ~BIT0);
REG_WRITE(regs->device_ready_reg, BIT0);
mdelay(1);
/*exit ULPS*/
if (__dpi_exit_ulps_locked(dsi_config)) {
DRM_ERROR("Failed to exit ULPS\n");
goto power_on_err;
}
/*update MIPI port config*/
REG_WRITE(regs->mipi_reg, (ctx->mipi | REG_READ(regs->mipi_reg)));
/*unready dsi adapter for re-programming*/
REG_WRITE(regs->device_ready_reg,
REG_READ(regs->device_ready_reg) & ~(DSI_DEVICE_READY));
/*D-PHY parameter*/
REG_WRITE(regs->dphy_param_reg, ctx->dphy_param);
/*Configure DSI controller*/
REG_WRITE(regs->mipi_control_reg, ctx->mipi_control);
REG_WRITE(regs->intr_en_reg, ctx->intr_en);
REG_WRITE(regs->hs_tx_timeout_reg, ctx->hs_tx_timeout);
REG_WRITE(regs->lp_rx_timeout_reg, ctx->lp_rx_timeout);
REG_WRITE(regs->turn_around_timeout_reg,
ctx->turn_around_timeout);
REG_WRITE(regs->device_reset_timer_reg,
ctx->device_reset_timer);
REG_WRITE(regs->high_low_switch_count_reg,
ctx->high_low_switch_count);
REG_WRITE(regs->init_count_reg, ctx->init_count);
REG_WRITE(regs->eot_disable_reg, ctx->eot_disable);
REG_WRITE(regs->lp_byteclk_reg, ctx->lp_byteclk);
REG_WRITE(regs->clk_lane_switch_time_cnt_reg,
ctx->clk_lane_switch_time_cnt);
if (ctx->pll_bypass_mode) {
/*Force using non-burst pulse event mode here*/
REG_WRITE(regs->video_mode_format_reg, 0x1);
} else {
REG_WRITE(regs->video_mode_format_reg, ctx->video_mode_format);
}
REG_WRITE(regs->dsi_func_prg_reg, ctx->dsi_func_prg);
/*DSI timing*/
REG_WRITE(regs->dpi_resolution_reg, ctx->dpi_resolution);
REG_WRITE(regs->hsync_count_reg, ctx->hsync_count);
REG_WRITE(regs->hbp_count_reg, ctx->hbp_count);
REG_WRITE(regs->hfp_count_reg, ctx->hfp_count);
REG_WRITE(regs->hactive_count_reg, ctx->hactive_count);
REG_WRITE(regs->vsync_count_reg, ctx->vsync_count);
REG_WRITE(regs->vbp_count_reg, ctx->vbp_count);
REG_WRITE(regs->vfp_count_reg, ctx->vfp_count);
/*Setup pipe timing*/
REG_WRITE(regs->htotal_reg, ctx->htotal);
REG_WRITE(regs->hblank_reg, ctx->hblank);
REG_WRITE(regs->hsync_reg, ctx->hsync);
REG_WRITE(regs->vtotal_reg, ctx->vtotal);
REG_WRITE(regs->vblank_reg, ctx->vblank);
REG_WRITE(regs->vsync_reg, ctx->vsync);
REG_WRITE(regs->pipesrc_reg, ctx->pipesrc);
REG_WRITE(regs->dsppos_reg, ctx->dsppos);
REG_WRITE(regs->dspstride_reg, ctx->dspstride);
/*Setup plane*/
REG_WRITE(regs->dspsize_reg, ctx->dspsize);
REG_WRITE(regs->dspsurf_reg, ctx->dspsurf);
REG_WRITE(regs->dsplinoff_reg, ctx->dsplinoff);
REG_WRITE(regs->vgacntr_reg, ctx->vgacntr);
/*restore color_coef (chrome) */
for (i = 0; i < 6; i++) {
REG_WRITE(regs->color_coef_reg + (i<<2), ctx->color_coef[i]);
}
/* restore palette (gamma) */
for (i = 0; i < 256; i++)
REG_WRITE(regs->palette_reg + (i<<2), ctx->palette[i]);
/* restore gamma correction max (RGB) */
REG_WRITE(regs->gamma_red_max_reg, ctx->gamma_red_max);
REG_WRITE(regs->gamma_green_max_reg, ctx->gamma_green_max);
REG_WRITE(regs->gamma_blue_max_reg, ctx->gamma_blue_max);
#ifdef CONFIG_CTP_DPST
/* restore dpst setting */
if (dev_priv->psb_dpst_state) {
dpstmgr_reg_restore_locked(dsi_config);
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
}
#endif
/*Enable DSI Controller*/
REG_WRITE(regs->device_ready_reg, (REG_READ(regs->device_ready_reg) | BIT0));
/**
* Different panel may have different ways to have
* drvIC initialized. Support it!
*/
if (p_funcs && p_funcs->drv_ic_init) {
if (p_funcs->drv_ic_init(dsi_config)) {
if (!reset_count) {
goto reset_err_bypass;
}
pmu_nc_set_power_state(OSPM_MIPI_ISLAND,
OSPM_ISLAND_DOWN, OSPM_REG_TYPE);
pmu_nc_set_power_state(OSPM_MIPI_ISLAND,
OSPM_ISLAND_UP, OSPM_REG_TYPE);
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
}
reset_err_bypass:
if (ctx->pll_bypass_mode) {
/*Reprogram to use pll clock*/
REG_WRITE(regs->dpll_reg, 0x0);
REG_WRITE(regs->fp_reg, 0x0);
REG_WRITE(regs->fp_reg, ctx->fp);
REG_WRITE(regs->dpll_reg, ((ctx->dpll) & ~BIT30));
udelay(2);
REG_WRITE(regs->dpll_reg, 0x2 << 17);
mdelay(1);
REG_WRITE(regs->dpll_reg, (0x2 << 17 | BIT31));
/*wait for PLL lock on pipe*/
retry = 10000;
while (--retry && !(REG_READ(PIPEACONF) & BIT29))
udelay(3);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
/*Switch back to burst mode*/
REG_WRITE(regs->video_mode_format_reg, ctx->video_mode_format);
/*Clear device ready reg*/
REG_WRITE(regs->device_ready_reg, REG_READ(regs->device_ready_reg) & ~DSI_DEVICE_READY);
msleep(1);
/*Enable DSI Controller*/
REG_WRITE(regs->device_ready_reg, REG_READ(regs->device_ready_reg) | DSI_DEVICE_READY);
msleep(1);
}
/**
* Different panel may have different ways to have
* panel turned on. Support it!
*/
if (p_funcs && p_funcs->power_on)
if (p_funcs->power_on(dsi_config)) {
DRM_ERROR("Failed to power on panel\n");
err = -EAGAIN;
goto power_on_err;
}
/*Enable MIPI Port*/
REG_WRITE(regs->mipi_reg, (ctx->mipi | BIT31));
/*Enable pipe*/
val = ctx->pipeconf;
val &= ~0x000c0000;
val |= BIT31;
/* disable gamma if needed */
if (drm_psb_enable_color_conversion == 0)
val &= ~(PIPEACONF_COLOR_MATRIX_ENABLE);
REG_WRITE(regs->pipeconf_reg, val);
REG_WRITE(regs->pipestat_reg, ctx->pipestat |
PIPE_VBLANK_INTERRUPT_ENABLE);
/*Wait for pipe enabling,when timing generator
is wroking */
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 10000;
while (--retry && !(REG_READ(regs->pipeconf_reg) & BIT30))
udelay(3);
if (!retry) {
DRM_ERROR("Failed to enable pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
/*enable plane*/
val = ctx->dspcntr | BIT31;
/* disable gamma if needed */
if (drm_psb_enable_gamma == 0)
val &= ~(PIPEACONF_GAMMA);
REG_WRITE(regs->dspcntr_reg, val);
/*Notify PVR module that screen is on*/
if (dev_priv->pvr_screen_event_handler)
dev_priv->pvr_screen_event_handler(dev, 1);
if (p_funcs && p_funcs->set_brightness)
if (p_funcs->set_brightness(dsi_config, ctx->lastbrightnesslevel))
DRM_ERROR("Failed to set panel brightness\n");
power_on_err:
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return err;
}
