/* Verify GDC, get memory size */
int gdc_post_test(int flags)
{
uint old_value;
int ret = 0;
post_log("\n");
old_value = in_be32((void *)GDC_SCRATCH_REG);
/*
* GPIOC2 register behaviour: the LIME graphics processor has a
* maximum of 5 GPIO ports that can be used in this hardware
* configuration. Thus only the bits for these 5 GPIOs can be
* activated in the GPIOC2 register. All other bits will always be
* read as zero.
*/
if (gdc_test_reg_one(0x00150015))
ret = 1;
if (gdc_test_reg_one(0x000A000A))
ret = 1;
out_be32((void *)GDC_SCRATCH_REG, old_value);
old_value = in_be32((void *)GDC_VERSION_REG);
post_log("GDC chip version %u.%u, year %04X\n",
(old_value >> 8) & 0xFF, old_value & 0xFF,
(old_value >> 16) & 0xFFFF);
old_value = get_ram_size((void *)GDC_RAM_START,
GDC_RAM_END - GDC_RAM_START);
post_log("GDC RAM size: %d bytes\n", old_value);
return ret;
}
int i2c_post_test (int flags)
{
unsigned int i;
#ifndef CONFIG_SYS_POST_I2C_ADDRS
/* Start at address 1, address 0 is the general call address */
for (i = 1; i < 128; i++) {
if (i2c_ignore_device(i))
continue;
if (i2c_probe (i) == 0)
return 0;
}
/* No devices found */
return -1;
#else
unsigned int ret = 0;
int j;
unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS;
/* Start at address 1, address 0 is the general call address */
for (i = 1; i < 128; i++) {
if (i2c_ignore_device(i))
continue;
if (i2c_probe(i) != 0)
continue;
for (j = 0; j < sizeof(i2c_addr_list); ++j) {
if (i == i2c_addr_list[j]) {
i2c_addr_list[j] = 0xff;
break;
}
}
if (j == sizeof(i2c_addr_list)) {
ret = -1;
post_log("I2C: addr %02x not expected\n", i);
}
}
for (i = 0; i < sizeof(i2c_addr_list); ++i) {
if (i2c_addr_list[i] == 0xff)
continue;
if (i2c_ignore_device(i2c_addr_list[i]))
continue;
post_log("I2C: addr %02x did not respond\n", i2c_addr_list[i]);
ret = -1;
}
return ret;
#endif
}
GNU_FPOST_ATTR
int fpu_post_test_math1 (void)
{
volatile double a, *p;
double c, d;
volatile double b;
d = 1.0;
p = &b;
do
{
c = d;
d = c * 0.5;
b = 1 + d;
} while (b != 1.0);
a = 1.0 + c;
if (a == 1.0) {
post_log ("Error in FPU math1 test\n");
return -1;
}
return 0;
}
GNU_FPOST_ATTR
int fpu_post_test_math4 (void)
{
volatile float reale = 1.0f;
volatile float oneplus;
int i;
if (sizeof (float) != 4)
return 0;
for (i = 0; ; i++)
{
oneplus = 1.0f + reale;
if (oneplus == 1.0f)
break;
reale = reale / 2.0f;
}
/* Assumes ieee754 accurate arithmetic above. */
if (i != 24) {
post_log ("Error in FPU math4 test\n");
return -1;
}
return 0;
}
static int test_ctlr (int ctlr, int index)
{
int res = -1;
char test_str[] = "*** UART Test String ***\r\n";
int i;
ctlr_proc[ctlr].init (index);
for (i = 0; i < sizeof (test_str) - 1; i++) {
ctlr_proc[ctlr].putc (index, test_str[i]);
if (ctlr_proc[ctlr].getc (index) != test_str[i])
goto Done;
}
res = 0;
Done:
ctlr_proc[ctlr].halt (index);
if (res != 0) {
post_log ("uart %s%d test failed\n",
ctlr_name[ctlr], index + 1);
}
return res;
}
int cpu_post_test_complex (void)
{
int ret = 0;
int flag = disable_interrupts();
if (ret == 0)
{
ret = cpu_post_test_complex_1();
}
if (ret == 0)
{
ret = cpu_post_test_complex_2();
}
if (ret != 0)
{
post_log ("Error at complex test !\n");
}
if (flag)
enable_interrupts();
return ret;
}
static int fpga_post_test1(ulong *start, ulong size, ulong val)
{
int ret = 0;
ulong i = 0;
ulong *mem = start;
ulong readback;
for (i = 0; i < size / sizeof(ulong); i++) {
mem[i] = val;
if (i % 1024 == 0)
WATCHDOG_RESET();
}
for (i = 0; i < size / sizeof(ulong); i++) {
readback = mem[i];
if (readback != val) {
post_log("FPGA Memory error at %08x, "
"wrote %08x, read %08x !\n",
mem + i, val, readback);
ret = -1;
break;
}
if (i % 1024 == 0)
WATCHDOG_RESET();
}
return ret;
}
int dsp_post_test(int flags)
{
uint old_value;
uint read_value;
int ret;
/* momorize fpga status */
old_value = in_be32((void *)FPGA_STATUS_REG);
/* enable outputs */
out_be32((void *)FPGA_STATUS_REG, 0x30);
/* generate sync signal */
out_be32((void *)DSP_STATUS_REG, 0x300);
udelay(5);
out_be32((void *)DSP_STATUS_REG, 0);
udelay(500);
/* read status */
ret = 0;
read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
if (read_value != 0x03) {
post_log("\nDSP status read %08X\n", read_value);
ret = 1;
}
/* restore fpga status */
out_be32((void *)FPGA_STATUS_REG, old_value);
return ret;
}
/* Verify FPGA addresslines */
static int fpga_post_dataline(ulong *address)
{
unsigned long temp32 = 0;
int i = 0;
int ret = 0;
for (i = 0; i < ARRAY_SIZE(pattern); i++) {
*address = pattern[i];
/*
* Put a different pattern on the data lines: otherwise they
* may float long enough to read back what we wrote.
*/
*(address + 1) = otherpattern;
temp32 = *address;
if (temp32 != pattern[i]){
post_log("Memory (date line) error at %08x, "
"wrote %08x, read %08x !\n",
address, pattern[i], temp32);
ret = 1;
}
}
return ret;
}
/* Verify FPGA addresslines */
static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
{
unsigned long *target;
unsigned long *end;
unsigned long readback;
unsigned long xor;
int ret = 0;
end = (ulong *)((ulong)base + size);
xor = 0;
for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
target = (ulong*)((ulong)address ^ xor);
if ((target >= base) && (target < end)) {
*address = ~*target;
readback = *target;
if (readback == *address) {
post_log("Memory (address line) error at %08x"
"XOR value %08x !\n",
address, target, xor);
ret = -1;
break;
}
}
}
return ret;
}
int sysmon1_post_test(int flags)
{
if (gpio_read_in_bit(CONFIG_SYS_GPIO_SYSMON_STATUS) == 0) {
/*
* 3.1. GPIO62 is low
* Assuming system voltage failure.
*/
post_log("sysmon1 Abnormal voltage detected (GPIO62)\n");
post_log("POST sysmon1 FAILED\n");
return 1;
} else {
post_log("sysmon1 PASSED\n");
}
return 0;
}
int spr_post_test (int flags)
{
int ret = 0;
int ic = icache_status ();
int i;
unsigned long code[] = {
0x7c6002a6, /* mfspr r3,SPR */
0x4e800020 /* blr */
};
unsigned long (*get_spr) (void) = (void *) code;
if (ic)
icache_disable ();
for (i = 0; i < spr_test_list_size; i++) {
int num = spr_test_list[i].number;
/* mfspr r3,num */
code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
if ((get_spr () & spr_test_list[i].mask) !=
(spr_test_list[i].value & spr_test_list[i].mask)) {
post_log ("The value of %s special register "
"is incorrect: 0x%08X\n",
spr_test_list[i].name, get_spr ());
ret = -1;
}
}
if (ic)
icache_enable ();
return ret;
}
//==============================================================
int l1cache_post_test(int flags)
{
int i;
unsigned result, pattern=0;
int status;
status = dcache_status();
if(dcache_status() == OFF)
dcache_enable();
dcache_flush();
icache_invalid();
dcache_clean();
dcache_disable();
// must invalid dcache after dcache_disable
// if no valid dcache, dcache_enable() will jump here
dcache_invalid();
asm("mov r0, r0");
asm("mov r0, r0");
asm("mov r0, r0");
for(i=0; i<ARRAY_SIZE(L1_cache_pattern); i++){
result = test_w_l1cache(0x55555555, L1_cache_pattern[i]);
if(result != 0){
pattern = L1_cache_pattern[i];
break;
}
result = test_w_l1cache(0x55555555, ~L1_cache_pattern[i]);
if(result != 0){
pattern = ~L1_cache_pattern[i];
break;
}
}
if(status == ON)
dcache_enable();
if(i<ARRAY_SIZE(L1_cache_pattern)){
post_log("<%d>%s:%d: l1cache: test fail: Error address=0x%x, pattern=0x%x\n", SYSTEST_INFO_L2,
__FUNCTION__, __LINE__, result, pattern);
return -1;
}
else{
post_log("<%d>l1cache test pattern count=%d\n", SYSTEST_INFO_L2, ARRAY_SIZE(L1_cache_pattern));
return 0;
}
}
int fpu_post_test_math2 (void)
{
if (rintf (-1.5) != -2.0) {
post_log ("Error in FPU math2 test\n");
return -1;
}
return 0;
}
//=======================================================================
int sdcard_post_test(int flags)
{
struct mmc *mmc;
int dev_num;
dev_num = simple_strtoul("mmcinfo", NULL, 0);
mmc = find_mmc_device(dev_num);
if (mmc) {
mmc_init(mmc);
if((mmc->tran_speed == 0) || (mmc->read_bl_len == 0) || (mmc->capacity == 0)) {
post_log("<%d>%s:%d: SDCARD: %s\n", SYSTEST_INFO_L2, __FUNCTION__, __LINE__, "no MMC device available.");
return -1;
}
post_log("<%d>SDCARD: Device: %s\n", SYSTEST_INFO_L2, mmc->name);
post_log("<%d>SDCARD: Manufacturer ID: %x\n", SYSTEST_INFO_L2, mmc->cid[0] >> 24);
post_log("<%d>SDCARD: OEM: %x\n", SYSTEST_INFO_L2, (mmc->cid[0] >> 8) & 0xffff);
//post_log("<%d>SDCARD: Name: %c%c%c%c%c\n",SYSTEST_INFO_L2, mmc->cid[0] & 0xff,
// (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
// (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
post_log("<%d>SDCARD: Tran Speed: %d\n", SYSTEST_INFO_L2, mmc->tran_speed);
post_log("<%d>SDCARD: Rd Block Len: %d\n", SYSTEST_INFO_L2, mmc->read_bl_len);
post_log("<%d>SDCARD: %s version %d.%d\n", SYSTEST_INFO_L2, IS_SD(mmc) ? "SD" : "MMC",
(mmc->version >> 4) & 0xf, mmc->version & 0xf);
post_log("<%d>SDCARD: High Capacity: %s\n", SYSTEST_INFO_L2, mmc->high_capacity ? "Yes" : "No");
post_log("<%d>SDCARD: Capacity: %lld\n", SYSTEST_INFO_L2, mmc->capacity);
post_log("<%d>SDCARD: Bus Width: %d-bit\n", SYSTEST_INFO_L2, mmc->bus_width);
}
else {
/* Verify that dsPIC ready test done early at hw init passed ok */
int dspic_init_post_test(int flags)
{
if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) &
CONFIG_SYS_DSPIC_TEST_MASK) {
post_log("dsPIC init test failed\n");
return 1;
}
return 0;
}
int fpu_post_test_math5 (void)
{
double values[] = { 0.1e-100, 1.0, -1.0, 0.0 };
if (func (values) != 0.1e-100) {
post_log ("Error in FPU math5 test\n");
return -1;
}
return 0;
}
int cpu_post_test_andi (void)
{
int ret = 0;
unsigned int i, reg;
int flag = disable_interrupts();
for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
{
struct cpu_post_andi_s *test = cpu_post_andi_table + i;
for (reg = 0; reg < 32 && ret == 0; reg++)
{
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
ASM_STW(3, stk, 8),
ASM_STW(reg0, stk, 4),
ASM_STW(reg1, stk, 0),
ASM_LWZ(reg0, stk, 8),
ASM_11IX(test->cmd, reg1, reg0, test->op2),
ASM_STW(reg1, stk, 8),
ASM_LWZ(reg1, stk, 0),
ASM_LWZ(reg0, stk, 4),
ASM_LWZ(3, stk, 8),
ASM_ADDI(1, stk, 16),
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
ulong res;
ulong cr;
cpu_post_exec_21 (codecr, & cr, & res, test->op1);
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
post_log ("Error at andi test %d !\n", i);
}
}
}
if (flag)
enable_interrupts();
return ret;
}
static int test_ctlr (int ctlr, int index)
{
int res = -1;
char packet_send[MAX_PACKET_LENGTH];
char packet_recv[MAX_PACKET_LENGTH];
int length;
int i;
int l;
ctlr_proc[ctlr].init (index);
for (i = 0; i < TEST_NUM; i++) {
for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
packet_fill (packet_send, l);
ctlr_proc[ctlr].send (index, packet_send, l);
length = ctlr_proc[ctlr].recv (index, packet_recv,
MAX_PACKET_LENGTH);
if (length != l || packet_check (packet_recv, length) < 0) {
goto Done;
}
}
}
res = 0;
Done:
ctlr_proc[ctlr].halt (index);
/*
* SCC2 Ethernet parameter RAM space overlaps
* the SPI parameter RAM space. So we need to restore
* the SPI configuration after SCC2 ethernet test.
*/
#if defined(CONFIG_SPI)
if (ctlr == CTLR_SCC && index == 1) {
spi_init_f ();
spi_init_r ();
}
#endif
if (res != 0) {
post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
index + 1);
}
return res;
}
int dsp_post_test(int flags)
{
uint read_value;
int ret;
ret = 0;
read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
if (read_value != 0x3) {
post_log("\nDSP status read %08X\n", read_value);
ret = 1;
}
return ret;
}
int fpu_post_test_math7 (void)
{
unsigned int i;
for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++)
{
tstmul (expected[i].p1, expected[i].p2, expected[i].res);
tstmul (expected[i].p2, expected[i].p1, expected[i].res);
}
if (!ok) {
post_log ("Error in FPU math7 test\n");
return -1;
}
return 0;
}
int fpu_post_test_math3 (void)
{
volatile long double dfrom = 1.1;
volatile long double m1;
volatile long double m2;
volatile unsigned long mant_long;
m1 = dfrom / 2.0;
m2 = m1 * 4294967296.0;
mant_long = ((unsigned long) m2) & 0xffffffff;
if (mant_long != 0x8ccccccc) {
post_log ("Error in FPU math3 test\n");
return -1;
}
return 0;
}
static int one_scratch_test(uint value)
{
uint read_value;
int ret = 0;
out_be32((void *)FPGA_SCRATCH_REG, value);
/* read other location (protect against data lines capacity) */
ret = in_be16((void *)FPGA_VERSION_REG);
/* verify test pattern */
read_value = in_be32((void *)FPGA_SCRATCH_REG);
if (read_value != value) {
post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
value, read_value);
ret = -1;
}
return ret;
}
static int gdc_test_reg_one(uint value)
{
int ret;
uint read_value;
/* write test pattern */
out_be32((void *)GDC_SCRATCH_REG, value);
/* read other location (protect against data lines capacity) */
ret = in_be32((void *)GDC_RAM_START);
/* verify test pattern */
read_value = in_be32((void *)GDC_SCRATCH_REG);
if (read_value != value) {
post_log("GDC SCRATCH test failed write %08X, read %08X\n",
value, read_value);
}
return (read_value != value);
}
//============================================================================
static int nand_sub_test(nand_info_t *nand, int idx)
{
if (!nand) {
nand_init();
if (!nand) {
post_log("<%d>%s:%d: NAND[device:%d]: no NAND device available.\n", SYSTEST_INFO_L2, __FUNCTION__, __LINE__, idx);
return -1;
}
}
if (nand->name) {
//struct nand_chip *chip = nand->priv;
/*#ifdef CONFIG_MTD_DEVICE
sprintf(systest_info_line, "NAND: Device %d: %s, %s sector size %u KiB \n", idx,
nand->name, nand->info, nand->erasesize >> 10);
systest_log(systest_info_line, SYSTEST_INFO_L2);
#else
*/
post_log("<%d>NAND: Device %d: %s, sector size %u KiB \n", SYSTEST_INFO_L2, idx, nand->name, nand->erasesize >> 10) ;
//#endif
}
static int test_ctlr (struct NS16550 *com_port, int index)
{
int res = -1;
char test_str[] = "*** UART Test String ***\r\n";
int i;
uart_post_init (com_port);
for (i = 0; i < sizeof (test_str) - 1; i++) {
uart_post_putc (com_port, test_str[i]);
if (uart_post_getc (com_port) != test_str[i])
goto done;
}
res = 0;
done:
if (res)
post_log ("uart%d test failed\n", index);
return res;
}
static int test_ctlr (unsigned long dev_base, int index)
{
int res = -1;
char test_str[] = "*** UART Test String ***\r\n";
int i;
uart_post_init (dev_base);
for (i = 0; i < sizeof (test_str) - 1; i++) {
uart_post_putc (dev_base, test_str[i]);
if (uart_post_getc (dev_base) != test_str[i])
goto done;
}
res = 0;
done:
if (res)
post_log ("uart%d test failed\n", index);
return res;
}
/* Verify error codes regs, display version */
int dspic_post_test(int flags)
{
ushort data;
int ret = 0;
post_log("\n");
/* read dspic FW-Version */
if (dspic_read(DSPIC_FW_VERSION_REG, &data)) {
post_log("dsPIC: failed read FW-Version\n");
ret = 1;
} else {
post_log("dsPIC FW-Version: %u.%u\n",
(data >> 8) & 0xFF, data & 0xFF);
}
/* read dspic SYS-Version */
if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) {
post_log("dsPIC: failed read version\n");
ret = 1;
} else {
post_log("dsPIC SYS-Version: %u.%u\n",
(data >> 8) & 0xFF, data & 0xFF);
}
/* read dspic POST error code */
if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
post_log("dsPIC: failed read POST code\n");
ret = 1;
} else {
post_log("dsPIC POST-ERROR code: 0x%04X\n", data);
}
/* read dspic SYS error code */
if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) {
post_log("dsPIC: failed read system error\n");
ret = 1;
} else {
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
}
return ret;
}
int spr_post_test (int flags)
{
int ret = 0;
int i;
unsigned long code[] = {
0x7c6002a6, /* mfspr r3,SPR */
0x4e800020 /* blr */
};
unsigned long (*get_spr) (void) = (void *) code;
#ifdef CONFIG_4xx_DCACHE
/* disable cache */
change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
#endif
for (i = 0; i < spr_test_list_size; i++) {
int num = spr_test_list[i].number;
/* mfspr r3,num */
code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
asm volatile ("isync");
if ((get_spr () & spr_test_list[i].mask) !=
(spr_test_list[i].value & spr_test_list[i].mask)) {
post_log ("The value of %s special register "
"is incorrect: 0x%08X\n",
spr_test_list[i].name, get_spr ());
ret = -1;
}
}
#ifdef CONFIG_4xx_DCACHE
/* enable cache */
change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
#endif
return ret;
}
int rtc_post_test (int flags)
{
ulong diff;
unsigned int i;
struct rtc_time svtm;
static unsigned int daysnl[] =
{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
static unsigned int daysl[] =
{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
unsigned int ynl = 1999;
unsigned int yl = 2000;
unsigned int skipped = 0;
int reliable;
/* Time reliability */
reliable = rtc_get (&svtm);
/* Time uniformity */
if (rtc_post_skip (&diff) != 0) {
post_log ("Timeout while waiting for a new second !\n");
return -1;
}
for (i = 0; i < 5; i++) {
if (rtc_post_skip (&diff) != 0) {
post_log ("Timeout while waiting for a new second !\n");
return -1;
}
if (diff < 950 || diff > 1050) {
post_log ("Invalid second duration !\n");
return -1;
}
}
/* Passing month boundaries */
if (rtc_post_skip (&diff) != 0) {
post_log ("Timeout while waiting for a new second !\n");
return -1;
}
rtc_get (&svtm);
for (i = 0; i < 12; i++) {
time_t t;
struct rtc_time tm;
tm.tm_year = ynl;
tm.tm_mon = i + 1;
tm.tm_mday = daysnl[i];
tm.tm_hour = 23;
tm.tm_min = 59;
tm.tm_sec = 59;
t = rtc_mktime(&tm);
rtc_to_tm(t, &tm);
rtc_set (&tm);
skipped++;
if (rtc_post_skip (&diff) != 0) {
rtc_post_restore (&svtm, skipped);
post_log ("Timeout while waiting for a new second !\n");
return -1;
}
rtc_get (&tm);
if (tm.tm_mon == i + 1) {
rtc_post_restore (&svtm, skipped);
post_log ("Month %d boundary is not passed !\n", i + 1);
return -1;
}
}
for (i = 0; i < 12; i++) {
time_t t;
struct rtc_time tm;
tm.tm_year = yl;
tm.tm_mon = i + 1;
tm.tm_mday = daysl[i];
tm.tm_hour = 23;
tm.tm_min = 59;
tm.tm_sec = 59;
t = rtc_mktime(&tm);
rtc_to_tm(t, &tm);
rtc_set (&tm);
skipped++;
if (rtc_post_skip (&diff) != 0) {
rtc_post_restore (&svtm, skipped);
post_log ("Timeout while waiting for a new second !\n");
return -1;
}
rtc_get (&tm);
if (tm.tm_mon == i + 1) {
rtc_post_restore (&svtm, skipped);
post_log ("Month %d boundary is not passed !\n", i + 1);
return -1;
}
}
rtc_post_restore (&svtm, skipped);
/* If come here, then RTC operates correcty, check the correctness
* of the time it reports.
*/
if (reliable < 0) {
post_log ("RTC Time is not reliable! Power fault? \n");
return -1;
}
return 0;
}
