/* * Enable (start) the DMA described by the sgl handle. */ void ppc4xx_enable_dma_sgl(sgl_handle_t handle) { sgl_list_info_t *psgl = (sgl_list_info_t *) handle; ppc_dma_ch_t *p_dma_ch; uint32_t sg_command; if (!handle) { printk("ppc4xx_enable_dma_sgl: null handle\n"); return; } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", psgl->dmanr); return; } else if (!psgl->phead) { printk("ppc4xx_enable_dma_sgl: sg list empty\n"); return; } p_dma_ch = &dma_channels[psgl->dmanr]; psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */ sg_command = mfdcr(DCRN_ASGC); ppc4xx_set_sg_addr(psgl->dmanr, psgl->phead_dma); sg_command |= SSG_ENABLE(psgl->dmanr); mtdcr(DCRN_ASGC, sg_command); /* start transfer */ }
/* * Enable (start) the DMA described by the sgl handle. */ static __inline__ void ppc4xx_enable_dma_sgl(sgl_handle_t handle) { sgl_list_info_t *psgl = (sgl_list_info_t *) handle; ppc_dma_ch_t *p_dma_ch; uint32_t sg_command; if (!handle) { printk("ppc4xx_enable_dma_sgl: null handle\n"); return; } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", psgl->dmanr); return; } else if (!psgl->phead) { printk("ppc4xx_enable_dma_sgl: sg list empty\n"); return; } p_dma_ch = &dma_channels[psgl->dmanr]; psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */ sg_command = mfdcr(DCRN_ASGC); ppc4xx_set_sg_addr(psgl->dmanr, iopa((unsigned long)psgl->phead)); switch (psgl->dmanr) { case 0: sg_command |= SSG0_ENABLE; break; case 1: sg_command |= SSG1_ENABLE; break; case 2: sg_command |= SSG2_ENABLE; break; case 3: sg_command |= SSG3_ENABLE; break; default: printk("ppc4xx_enable_dma_sgl: bad channel: %d\n", psgl->dmanr); } mtdcr(DCRN_ASGC, sg_command); /* start transfer */ }