/* Initialize all the register values. Do the initial setup
* calculations for interpolants.
*/
static void init_registers( struct brw_wm_compile *c )
{
GLuint reg = 0;
GLuint j;
for (j = 0; j < c->grf_limit; j++)
c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
/* Pre-allocate incoming payload regs:
*/
for (j = 0; j < c->key.nr_depth_regs; j++)
prealloc_reg(c, &c->payload.depth[j], reg++);
for (j = 0; j < c->nr_creg; j++)
prealloc_reg(c, &c->creg[j], reg++);
reg++; /* XXX: skip over position output */
/* XXX: currently just hope the VS outputs line up with FS inputs:
*/
for (j = 0; j < c->key.nr_inputs; j++)
prealloc_reg(c, &c->payload.input_interp[j], reg++);
c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
c->prog_data.urb_read_length = (c->key.nr_inputs + 1) * 2;
c->prog_data.curb_read_length = c->nr_creg * 2;
/* Note this allocation:
*/
c->max_wm_grf = reg * 2;
}
/* Initialize all the register values. Do the initial setup
* calculations for interpolants.
*/
static void init_registers( struct brw_wm_compile *c )
{
struct brw_context *brw = c->func.brw;
struct intel_context *intel = &brw->intel;
GLuint nr_interp_regs = 0;
GLuint i = 0;
GLuint j;
for (j = 0; j < c->grf_limit; j++)
c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++)
prealloc_reg(c, &c->payload.depth[j], i++);
for (j = 0; j < c->nr_creg; j++)
prealloc_reg(c, &c->creg[j], i++);
if (intel->gen >= 6) {
for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) {
if (c->fp->program.Base.InputsRead & BITFIELD64_BIT(j)) {
nr_interp_regs++;
prealloc_reg(c, &c->payload.input_interp[j], i++);
}
}
} else {
for (j = 0; j < VERT_RESULT_MAX; j++) {
/* Point size is packed into the header, not as a general attribute */
if (j == VERT_RESULT_PSIZ)
continue;
if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
int fp_index = _mesa_vert_result_to_frag_attrib(j);
nr_interp_regs++;
/* The back color slot is skipped when the front color is
* also written to. In addition, some slots can be
* written in the vertex shader and not read in the
* fragment shader. So the register number must always be
* incremented, mapped or not.
*/
if (fp_index >= 0)
prealloc_reg(c, &c->payload.input_interp[fp_index], i);
i++;
}
}
assert(nr_interp_regs >= 1);
}
c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2);
c->prog_data.urb_read_length = nr_interp_regs * 2;
c->prog_data.curb_read_length = c->nr_creg * 2;
c->max_wm_grf = i * 2;
}
static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
{
#define MAX_IFSN 32
#define MAX_LOOP_DEPTH 32
struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH];
struct brw_instruction *inst0, *inst1;
int i, if_insn = 0, loop_insn = 0;
struct brw_compile *p = &c->func;
struct brw_indirect stack_index = brw_indirect(0, 0);
c->reg_index = 0;
prealloc_reg(c);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
for (i = 0; i < c->nr_fp_insns; i++) {
struct prog_instruction *inst = &c->prog_instructions[i];
struct prog_instruction *orig_inst;
if ((orig_inst = inst->Data) != 0)
orig_inst->Data = current_insn(p);
if (inst->CondUpdate)
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
else
brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
switch (inst->Opcode) {
case WM_PIXELXY:
emit_pixel_xy(c, inst);
break;
case WM_DELTAXY:
emit_delta_xy(c, inst);
break;
case WM_PIXELW:
emit_pixel_w(c, inst);
break;
case WM_LINTERP:
emit_linterp(c, inst);
break;
case WM_PINTERP:
emit_pinterp(c, inst);
break;
case WM_CINTERP:
emit_cinterp(c, inst);
break;
case WM_WPOSXY:
emit_wpos_xy(c, inst);
break;
case WM_FB_WRITE:
emit_fb_write(c, inst);
break;
case OPCODE_ABS:
emit_abs(c, inst);
break;
case OPCODE_ADD:
emit_add(c, inst);
break;
case OPCODE_SUB:
emit_sub(c, inst);
break;
case OPCODE_FRC:
emit_frc(c, inst);
break;
case OPCODE_FLR:
emit_flr(c, inst);
break;
case OPCODE_LRP:
emit_lrp(c, inst);
break;
case OPCODE_INT:
emit_int(c, inst);
break;
case OPCODE_MOV:
emit_mov(c, inst);
break;
case OPCODE_DP3:
emit_dp3(c, inst);
break;
case OPCODE_DP4:
emit_dp4(c, inst);
break;
case OPCODE_XPD:
emit_xpd(c, inst);
break;
case OPCODE_DPH:
emit_dph(c, inst);
break;
case OPCODE_RCP:
emit_rcp(c, inst);
break;
case OPCODE_RSQ:
emit_rsq(c, inst);
break;
case OPCODE_SIN:
emit_sin(c, inst);
break;
case OPCODE_COS:
emit_cos(c, inst);
break;
case OPCODE_EX2:
emit_ex2(c, inst);
break;
case OPCODE_LG2:
emit_lg2(c, inst);
break;
case OPCODE_MAX:
emit_max(c, inst);
break;
case OPCODE_MIN:
emit_min(c, inst);
break;
case OPCODE_DDX:
emit_ddx(c, inst);
break;
case OPCODE_DDY:
emit_ddy(c, inst);
break;
case OPCODE_SLT:
emit_slt(c, inst);
break;
case OPCODE_SLE:
emit_sle(c, inst);
break;
case OPCODE_SGT:
emit_sgt(c, inst);
break;
case OPCODE_SGE:
emit_sge(c, inst);
break;
case OPCODE_SEQ:
emit_seq(c, inst);
break;
case OPCODE_SNE:
emit_sne(c, inst);
break;
case OPCODE_MUL:
emit_mul(c, inst);
break;
case OPCODE_POW:
emit_pow(c, inst);
break;
case OPCODE_MAD:
emit_mad(c, inst);
break;
case OPCODE_TEX:
emit_tex(c, inst);
break;
case OPCODE_TXB:
emit_txb(c, inst);
break;
case OPCODE_KIL_NV:
emit_kil(c);
break;
case OPCODE_IF:
assert(if_insn < MAX_IFSN);
if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
break;
case OPCODE_ELSE:
if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
break;
case OPCODE_ENDIF:
assert(if_insn > 0);
brw_ENDIF(p, if_inst[--if_insn]);
break;
case OPCODE_BGNSUB:
case OPCODE_ENDSUB:
break;
case OPCODE_CAL:
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(4));
orig_inst = inst->Data;
orig_inst->Data = &p->store[p->nr_insn];
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
brw_pop_insn_state(p);
break;
case OPCODE_RET:
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(-4));
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
break;
case OPCODE_BGNLOOP:
loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8);
break;
case OPCODE_BRK:
brw_BREAK(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
case OPCODE_CONT:
brw_CONT(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
case OPCODE_ENDLOOP:
loop_insn--;
inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]);
/* patch all the BREAK instructions from
last BEGINLOOP */
while (inst0 > loop_inst[loop_insn]) {
inst0--;
if (inst0->header.opcode == BRW_OPCODE_BREAK) {
inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
inst0->bits3.if_else.pop_count = 0;
} else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
inst0->bits3.if_else.jump_count = inst1 - inst0;
inst0->bits3.if_else.pop_count = 0;
}
}
break;
default:
_mesa_printf("unsupported IR in fragment shader %d\n",
inst->Opcode);
}
if (inst->CondUpdate)
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
else
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
post_wm_emit(c);
for (i = 0; i < c->fp->program.Base.NumInstructions; i++)
c->fp->program.Base.Instructions[i].Data = NULL;
}
