static CResult
list_controls (CHandle hDevice)
{
CResult ret;
unsigned int count = 0;
CControl *controls = NULL;
// Retrieve the control list
ret = get_control_list(hDevice, &controls, &count);
if(ret) goto done;
if(count == 0) {
printf("No controls found.\n");
goto done;
}
// Print a list of all available controls
for(int i = 0; i < count; i++) {
CControl *control = &controls[i];
print_control(control);
}
done:
if(controls) free(controls);
if(ret)
print_handle_error(hDevice, "Unable to retrieve device list", ret);
return ret;
}
static int
_x86_start( hwd_context_t * ctx, hwd_control_state_t * state )
{
int error;
#ifdef DEBUG
print_control( &state->control.cpu_control );
#endif
if ( state->rvperfctr != NULL ) {
if ( ( error =
rvperfctr_control( state->rvperfctr, &state->control ) ) < 0 ) {
SUBDBG( "rvperfctr_control returns: %d\n", error );
PAPIERROR( RCNTRL_ERROR );
return ( PAPI_ESYS );
}
return ( PAPI_OK );
}
if ( ( error = vperfctr_control( ctx->perfctr, &state->control ) ) < 0 ) {
SUBDBG( "vperfctr_control returns: %d\n", error );
PAPIERROR( VCNTRL_ERROR );
return ( PAPI_ESYS );
}
return ( PAPI_OK );
}
static void list_controls(int fd, int show_menus)
{
struct v4l2_queryctrl qctrl = { V4L2_CTRL_FLAG_NEXT_CTRL };
int id;
while (ioctl(fd, VIDIOC_QUERYCTRL, &qctrl) == 0) {
print_control(fd, qctrl, show_menus);
qctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL;
}
if (qctrl.id != V4L2_CTRL_FLAG_NEXT_CTRL)
return;
for (id = V4L2_CID_USER_BASE; id < V4L2_CID_LASTP1; id++) {
qctrl.id = id;
if (ioctl(fd, VIDIOC_QUERYCTRL, &qctrl) == 0)
print_control(fd, qctrl, show_menus);
}
for (qctrl.id = V4L2_CID_PRIVATE_BASE;
ioctl(fd, VIDIOC_QUERYCTRL, &qctrl) == 0; qctrl.id++) {
print_control(fd, qctrl, show_menus);
}
}
static void list_controls(int fd, int show_menus)
{
const unsigned next_fl = V4L2_CTRL_FLAG_NEXT_CTRL | V4L2_CTRL_FLAG_NEXT_COMPOUND;
struct v4l2_query_ext_ctrl qctrl;
int id;
memset(&qctrl, 0, sizeof(qctrl));
qctrl.id = next_fl;
while (query_ext_ctrl_ioctl(fd, qctrl) == 0) {
print_control(fd, qctrl, show_menus);
qctrl.id |= next_fl;
}
if (!(qctrl.id & next_fl))
return;
for (id = V4L2_CID_USER_BASE; id < V4L2_CID_LASTP1; id++) {
qctrl.id = id;
if (query_ext_ctrl_ioctl(fd, qctrl) == 0)
print_control(fd, qctrl, show_menus);
}
for (qctrl.id = V4L2_CID_PRIVATE_BASE;
query_ext_ctrl_ioctl(fd, qctrl) == 0; qctrl.id++) {
print_control(fd, qctrl, show_menus);
}
}
static void
clear_cs_events( hwd_control_state_t * this_state )
{
unsigned int i, j;
/* total counters is sum of accumulating (nractrs) and interrupting (nrictrs) */
j = this_state->control.cpu_control.nractrs +
this_state->control.cpu_control.nrictrs;
/* Remove all counter control command values from eventset. */
for ( i = 0; i < j; i++ ) {
SUBDBG( "Clearing pmc event entry %d\n", i );
if ( is_pentium4() ) {
this_state->control.cpu_control.pmc_map[i] = 0;
this_state->control.cpu_control.evntsel[i] = 0;
this_state->control.cpu_control.evntsel_aux[i] =
this_state->control.cpu_control.
evntsel_aux[i] & ( ESCR_T0_OS | ESCR_T0_USR );
} else {
this_state->control.cpu_control.pmc_map[i] = i;
this_state->control.cpu_control.evntsel[i]
= this_state->control.cpu_control.
evntsel[i] & ( PERF_ENABLE | PERF_OS | PERF_USR );
}
this_state->control.cpu_control.ireset[i] = 0;
}
if ( is_pentium4() ) {
/* Clear pebs stuff */
this_state->control.cpu_control.p4.pebs_enable = 0;
this_state->control.cpu_control.p4.pebs_matrix_vert = 0;
}
/* clear both a and i counter counts */
this_state->control.cpu_control.nractrs = 0;
this_state->control.cpu_control.nrictrs = 0;
#ifdef DEBUG
if ( is_pentium4() )
print_control( &this_state->control.cpu_control );
#endif
}
PROCESS_THREAD(default_app_process, ev, data) {
uip_ipaddr_t ipaddr;
PROCESS_BEGIN();
set_connection_address(&ipaddr);
/* new connection with remote host */
client_conn = udp_new(&ipaddr, UIP_HTONS(3002), NULL);
udp_bind(client_conn, UIP_HTONS(3003));
PRINTF("Created a connection with the server ");
PRINT6ADDR(&client_conn->ripaddr);
PRINTF(" local/remote port %u/%u\n",
UIP_HTONS(client_conn->lport), UIP_HTONS(client_conn->rport));
SENSORS_ACTIVATE(acc_sensor);
etimer_set(&timer, CLOCK_SECOND * 0.05);
printf("Node configured as ");
print_control();
printf("\n");
while (1) {
PROCESS_YIELD();
if ( etimer_expired(&timer) ) {
etimer_set(&timer, CLOCK_SECOND*0.05);
x = acc_sensor.value(ACC_Y_RAW);
if (x > 380) {
//send
udp_send_data();
etimer_set(&timer, CLOCK_SECOND*0.3);
count++;
}
}
}
PROCESS_END();
}
/* Collected wisdom indicates that each call to pmc_set_control will write 0's
into the hardware counters, effecting a reset operation.
*/
int
_papi_hwd_start( hwd_context_t * ctx, hwd_control_state_t * spc )
{
int error;
struct pmc_control *ctl =
( struct pmc_control * ) ( spc->control.cpu_control.evntsel );
/* clear the accumulating counter values */
memset( ( void * ) spc->state.sum.pmc, 0,
_papi_hwi_system_info.num_cntrs * sizeof ( long long ) );
if ( ( error = pmc_set_control( ctx->self, ctl ) ) < 0 ) {
SUBDBG( "pmc_set_control returns: %d\n", error );
{
PAPIERROR( "pmc_set_control() returned < 0" );
return ( PAPI_ESYS );
}
}
#ifdef DEBUG
print_control( &spc->control.cpu_control );
#endif
return ( PAPI_OK );
}
int
_papi_hwd_start( hwd_context_t * ctx, hwd_control_state_t * state )
{
int error;
/* clear_unused_pmcsel_bits(this_state); moved to update_control_state */
#ifdef DEBUG
print_control( &state->control.cpu_control );
#endif
if ( state->rvperfctr != NULL ) {
if ( ( error =
rvperfctr_control( state->rvperfctr, &state->control ) ) < 0 ) {
SUBDBG( "rvperfctr_control returns: %d\n", error );
PAPIERROR( RCNTRL_ERROR );
return ( PAPI_ESYS );
}
return ( PAPI_OK );
}
if ( ( error = vperfctr_control( ctx->perfctr, &state->control ) ) < 0 ) {
SUBDBG( "vperfctr_control returns: %d\n", error );
PAPIERROR( VCNTRL_ERROR );
return ( PAPI_ESYS );
}
return ( PAPI_OK );
}
int
_papi_hwd_set_overflow( EventSetInfo_t * ESI, int EventIndex, int threshold )
{
hwd_control_state_t *this_state = &ESI->machdep;
struct hwd_pmc_control *contr = &this_state->control;
int i, ncntrs, nricntrs = 0, nracntrs = 0, retval = 0;
OVFDBG( "EventIndex=%d, threshold = %d\n", EventIndex, threshold );
/* The correct event to overflow is EventIndex */
ncntrs = _papi_hwi_system_info.sub_info.num_cntrs;
i = ESI->EventInfoArray[EventIndex].pos[0];
if ( i >= ncntrs ) {
OVFDBG( "Selector id (%d) larger than ncntrs (%d)\n", i, ncntrs );
return PAPI_EINVAL;
}
if ( threshold != 0 ) { /* Set an overflow threshold */
if ( ESI->EventInfoArray[EventIndex].derived ) {
OVFDBG( "Can't overflow on a derived event.\n" );
return PAPI_EINVAL;
}
if ( ( retval =
_papi_hwi_start_signal( _papi_hwi_system_info.sub_info.
hardware_intr_sig,
NEED_CONTEXT ) ) != PAPI_OK )
return ( retval );
contr->cpu_control.ireset[i] = PMC_OVFL - threshold;
nricntrs = ++contr->cpu_control.nrictrs;
nracntrs = --contr->cpu_control.nractrs;
contr->si_signo = _papi_hwi_system_info.sub_info.hardware_intr_sig;
contr->cpu_control.ppc64.mmcr0 |= PERF_INT_ENABLE;
/* move this event to the bottom part of the list if needed */
if ( i < nracntrs )
swap_events( ESI, contr, i, nracntrs );
OVFDBG( "Modified event set\n" );
} else {
if ( contr->cpu_control.ppc64.mmcr0 & PERF_INT_ENABLE ) {
contr->cpu_control.ireset[i] = 0;
nricntrs = --contr->cpu_control.nrictrs;
nracntrs = ++contr->cpu_control.nractrs;
if ( !nricntrs )
contr->cpu_control.ppc64.mmcr0 &= ( ~PERF_INT_ENABLE );
}
/* move this event to the top part of the list if needed */
if ( i >= nracntrs )
swap_events( ESI, contr, i, nracntrs - 1 );
if ( !nricntrs )
contr->si_signo = 0;
OVFDBG( "Modified event set\n" );
retval =
_papi_hwi_stop_signal( _papi_hwi_system_info.sub_info.
hardware_intr_sig );
}
#ifdef DEBUG
print_control( &contr->cpu_control );
#endif
OVFDBG( "%s:%d: Hardware overflow is still experimental.\n", __FILE__,
__LINE__ );
OVFDBG( "End of call. Exit code: %d\n", retval );
return ( retval );
}
int
tel_getdata(void)
{
int i;
int ret;
struct buffer *bp = Nvt.inbuff;
unsigned char c;
if ((ret = sock_read(Comibuf, Nvt.iosize)) <= 0)
return -1;
if (Debug > 2) {
sysmessage(MSG_DEBUG,
"Sock_read, %d bytes: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ret, Comibuf[0], Comibuf[1], Comibuf[2], Comibuf[3],
Comibuf[4], Comibuf[5], Comibuf[6], Comibuf[7]);
}
if (Nvt.servertype == SRV_SOCKET) {
COPY_TO_BUFFER(bp, Comibuf, ret);
SET_EVENT(EV_RN, EV_RNDATA, 0, 0);
return (0);
}
for (i = 0; i < ret; i++) {
c = Comibuf[i];
switch (S_state) {
case S_DATA:
if (c == IAC) {
S_state = S_IAC;
print_control(c);
}
else {
PUT_BUFFER(bp, c);
/* Event EV_RNDATA will be set at end */
}
break;
case S_IAC:
switch (c) {
case DO:
S_state = S_DO;
print_control(c);
break;
case DONT:
S_state = S_DONT;
print_control(c);
break;
case WILL:
S_state = S_WILL;
print_control(c);
break;
case WONT:
S_state = S_WONT;
print_control(c);
break;
case SB:
S_state = S_SB;
print_control(c);
Suboptsize = 0;
break;
case IAC:
default:
S_state = S_DATA;
PUT_BUFFER(bp, c);
break;
}
break;
case S_DO:
print_option(c);
S_state = S_DATA;
do_option(c);
break;
case S_DONT:
print_option(c);
S_state = S_DATA;
dont_option(c);
break;
case S_WILL:
print_option(c);
S_state = S_DATA;
will_option(c);
break;
case S_WONT:
print_option(c);
S_state = S_DATA;
wont_option(c);
break;
case S_SB:
if (c == IAC) {
S_state = S_SE;
print_control(c);
}
else {
if (Suboptsize > SUBOPT_MAXSIZE) {
sysmessage(MSG_WARNING, "Suboption too large\n");
}
else {
Suboptbuf[Suboptsize++] = c;
}
}
break;
case S_SE:
if (c == SE) {
S_state = S_DATA;
print_control(c);
handle_suboption(Suboptbuf, Suboptsize);
Suboptsize = 0;
}
else {
S_state = S_DATA;
sysmessage(MSG_WARNING, "Suboption not terminated: %d", c);
}
break;
}
}
if (bp->b_hold) {
SET_EVENT(EV_RN, EV_RNDATA, 0, 0);
}
print_all();
return (0);
}
static int
_x86_set_overflow( EventSetInfo_t * ESI, int EventIndex, int threshold )
{
struct hwd_pmc_control *contr = &ESI->ctl_state->control;
int i, ncntrs, nricntrs = 0, nracntrs = 0, retval = 0;
OVFDBG( "EventIndex=%d\n", EventIndex );
#ifdef DEBUG
if ( is_pentium4() )
print_control( &ESI->ctl_state->control.cpu_control );
#endif
/* The correct event to overflow is EventIndex */
ncntrs = MY_VECTOR.cmp_info.num_cntrs;
i = ESI->EventInfoArray[EventIndex].pos[0];
if ( i >= ncntrs ) {
PAPIERROR( "Selector id %d is larger than ncntrs %d", i, ncntrs );
return PAPI_EINVAL;
}
if ( threshold != 0 ) { /* Set an overflow threshold */
retval = _papi_hwi_start_signal( MY_VECTOR.cmp_info.hardware_intr_sig,
NEED_CONTEXT,
MY_VECTOR.cmp_info.CmpIdx );
if ( retval != PAPI_OK )
return ( retval );
/* overflow interrupt occurs on the NEXT event after overflow occurs
thus we subtract 1 from the threshold. */
contr->cpu_control.ireset[i] = ( -threshold + 1 );
if ( is_pentium4() )
contr->cpu_control.evntsel[i] |= CCCR_OVF_PMI_T0;
else
contr->cpu_control.evntsel[i] |= PERF_INT_ENABLE;
contr->cpu_control.nrictrs++;
contr->cpu_control.nractrs--;
nricntrs = ( int ) contr->cpu_control.nrictrs;
nracntrs = ( int ) contr->cpu_control.nractrs;
contr->si_signo = MY_VECTOR.cmp_info.hardware_intr_sig;
/* move this event to the bottom part of the list if needed */
if ( i < nracntrs )
swap_events( ESI, contr, i, nracntrs );
OVFDBG( "Modified event set\n" );
} else {
if ( is_pentium4() && contr->cpu_control.evntsel[i] & CCCR_OVF_PMI_T0 ) {
contr->cpu_control.ireset[i] = 0;
contr->cpu_control.evntsel[i] &= ( ~CCCR_OVF_PMI_T0 );
contr->cpu_control.nrictrs--;
contr->cpu_control.nractrs++;
} else if ( !is_pentium4() &&
contr->cpu_control.evntsel[i] & PERF_INT_ENABLE ) {
contr->cpu_control.ireset[i] = 0;
contr->cpu_control.evntsel[i] &= ( ~PERF_INT_ENABLE );
contr->cpu_control.nrictrs--;
contr->cpu_control.nractrs++;
}
nricntrs = ( int ) contr->cpu_control.nrictrs;
nracntrs = ( int ) contr->cpu_control.nractrs;
/* move this event to the top part of the list if needed */
if ( i >= nracntrs )
swap_events( ESI, contr, i, nracntrs - 1 );
if ( !nricntrs )
contr->si_signo = 0;
OVFDBG( "Modified event set\n" );
retval = _papi_hwi_stop_signal( MY_VECTOR.cmp_info.hardware_intr_sig );
}
#ifdef DEBUG
if ( is_pentium4() )
print_control( &ESI->ctl_state->control.cpu_control );
#endif
OVFDBG( "End of call. Exit code: %d\n", retval );
return ( retval );
}
/* This function clears the current contents of the control structure and
updates it with whatever resources are allocated for all the native events
in the native info structure array. */
static int
_x86_update_control_state( hwd_control_state_t * this_state,
NativeInfo_t * native, int count,
hwd_context_t * ctx )
{
( void ) ctx; /*unused */
unsigned int i, k, retval = PAPI_OK;
hwd_register_t *bits;
struct perfctr_cpu_control *cpu_control = &this_state->control.cpu_control;
/* clear out the events from the control state */
clear_cs_events( this_state );
if ( is_pentium4() ) {
/* fill the counters we're using */
for ( i = 0; i < ( unsigned int ) count; i++ ) {
/* dereference the mapping information about this native event */
bits = native[i].ni_bits;
/* Add counter control command values to eventset */
cpu_control->pmc_map[i] = bits->counter[0];
cpu_control->evntsel[i] = bits->cccr;
cpu_control->ireset[i] = bits->ireset;
cpu_control->pmc_map[i] |= FAST_RDPMC;
cpu_control->evntsel_aux[i] |= bits->event;
/* pebs_enable and pebs_matrix_vert are shared registers used for replay_events.
Replay_events count L1 and L2 cache events. There is only one of each for
the entire eventset. Therefore, there can be only one unique replay_event
per eventset. This means L1 and L2 can't be counted together. Which stinks.
This conflict should be trapped in the allocation scheme, but we'll test for it
here too, just in case. */
if ( bits->pebs_enable ) {
/* if pebs_enable isn't set, just copy */
if ( cpu_control->p4.pebs_enable == 0 ) {
cpu_control->p4.pebs_enable = bits->pebs_enable;
/* if pebs_enable conflicts, flag an error */
} else if ( cpu_control->p4.pebs_enable != bits->pebs_enable ) {
SUBDBG
( "WARNING: P4_update_control_state -- pebs_enable conflict!" );
retval = PAPI_ECNFLCT;
}
/* if pebs_enable == bits->pebs_enable, do nothing */
}
if ( bits->pebs_matrix_vert ) {
/* if pebs_matrix_vert isn't set, just copy */
if ( cpu_control->p4.pebs_matrix_vert == 0 ) {
cpu_control->p4.pebs_matrix_vert = bits->pebs_matrix_vert;
/* if pebs_matrix_vert conflicts, flag an error */
} else if ( cpu_control->p4.pebs_matrix_vert !=
bits->pebs_matrix_vert ) {
SUBDBG
( "WARNING: P4_update_control_state -- pebs_matrix_vert conflict!" );
retval = PAPI_ECNFLCT;
}
/* if pebs_matrix_vert == bits->pebs_matrix_vert, do nothing */
}
}
this_state->control.cpu_control.nractrs = count;
/* Make sure the TSC is always on */
this_state->control.cpu_control.tsc_on = 1;
#ifdef DEBUG
print_control( &this_state->control.cpu_control );
#endif
} else {
switch ( _papi_hwi_system_info.hw_info.model ) {
#ifdef PERFCTR_X86_INTEL_CORE2
case PERFCTR_X86_INTEL_CORE2:
/* fill the counters we're using */
for ( i = 0; i < ( unsigned int ) count; i++ ) {
for ( k = 0; k < MAX_COUNTERS; k++ )
if ( native[i].ni_bits->selector & ( 1 << k ) ) {
break;
}
if ( k > 1 )
this_state->control.cpu_control.pmc_map[i] =
( k - 2 ) | 0x40000000;
else
this_state->control.cpu_control.pmc_map[i] = k;
/* Add counter control command values to eventset */
this_state->control.cpu_control.evntsel[i] |=
native[i].ni_bits->counter_cmd;
}
break;
#endif
default:
/* fill the counters we're using */
for ( i = 0; i < ( unsigned int ) count; i++ ) {
/* Add counter control command values to eventset */
this_state->control.cpu_control.evntsel[i] |=
native[i].ni_bits->counter_cmd;
}
}
this_state->control.cpu_control.nractrs = ( unsigned int ) count;
}
return retval;
}