/*******************************************************************************
raw_istream
*******************************************************************************/
raw_istream &raw_istream::read(void *buffer, size_t size)
{
_last_read = 0 ;
if (rdstate() & (eofbit|badbit))
raw_ios::resetstate(rdstate()) ;
else
{
setstate_nothrow(failbit, false) ;
if (!size)
return *this ;
try {
// Temporary mask all exceptions
sentry guard(*this) ;
_last_read = do_read(buffer, size) ;
setstate_nothrow(external_state(), true) ;
NOXCHECK(_last_read <= size) ;
}
catch(...)
{
process_exception() ;
return *this ;
}
// Throw pending exceptions, if present
unsigned newstate = rdstate() ;
if (_last_read < size)
newstate |= failbit ;
if (newstate)
resetstate(newstate) ;
}
return *this ;
}
/*******************************************************************************
raw_ostream
*******************************************************************************/
raw_ostream &raw_ostream::write(const void *buffer, size_t size)
{
_last_written = 0 ;
if (rdstate() & ~failbit)
raw_ios::resetstate(rdstate()) ;
else
{
setstate_nothrow(failbit, false) ;
if (!size)
return *this ;
try {
// Temporary mask all exceptions
sentry guard(*this) ;
_last_written = do_write(buffer, size) ;
setstate_nothrow(external_state(), true) ;
NOXCHECK(_last_written <= size) ;
}
catch(...)
{
process_exception() ;
return *this ;
}
// Throw pending exceptions, if present
resetstate(rdstate() | (_last_written < size ? (unsigned)failbit : 0)) ;
}
return *this ;
}
static void
gs32eb1_io_do_cycle (void * state)
{
MIPS_State* mstate = get_current_core();
#if 1
if(!(mstate->cp0[Cause] & (1 << Cause_IP4))){
/* UART receive interrupt enable */
int uart_int_enable = ((mstate->cp0[SR] & (1 << SR_IM4)) >> SR_IM4) & (mstate->cp0[SR] & (1 << SR_IEC)); // UART interrupt enable
struct timeval tv;
unsigned char c;
tv.tv_sec = 0;
tv.tv_usec = 0;
if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0)
{
io.uart[0].thr = (int) c;
//printf("SKYEYE: io_do_cycle set intcause = %x\n",io.uart[0].intcause);
io.uart[0].lsr |= 0x01; //Data ready
//printf("In %s, uart receive int,uart_int_enable=0x%x, SR=0x%x\n", __FUNCTION__, uart_int_enable, mstate->cp0[SR]);
io.uart[0].iir |= 0x4; //Rx idle
} /* if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0) */
// UART interrupt enable
if(uart_int_enable){
if ((io.uart[0].ier & 0x1)
&& (io.uart[0].iir & 0x4)) {
io.uart[0].iir &= ~0x1;
/* Set uart interrupt bit in IP section of Cause register */
mstate->cp0[Cause] |= 1 << Cause_IP4;
/* Set ExcCode to zero in Cause register */
process_exception(mstate, EXC_Int, common_vector);
}
#if 1
if (io.uart[0].ier & 0x2) {
io.uart[0].iir |= 0x2;
io.uart[0].iir &= ~0x1;
io.uart[0].lsr |= 0x60;
//printf("THR interrupt\n");
/* Set uart interrupt bit in IP section of Cause register */
mstate->cp0[Cause] |= 1 << Cause_IP4;
/* Set ExcCode to zero in Cause register */
process_exception(mstate, EXC_Int, common_vector);
}
#endif
}
}
static void update_int(){
MIPS_State* mstate = get_current_core();
if(io.int_ctrl[0].req0int & 0x1){
//printf("hardware int happened!\n");
mstate->cp0[Cause] |= 1 << Cause_IP2;
process_exception(mstate, EXC_Int, common_vector);
}
}
extern "C" void FaultHandler( void )
{
volatile unsigned int i=1;
process_exception();
if(restart_on_exception)
{
// stop systick
SYST->SYST_CSR = 0;
LowLevelReboot();
}
while(i){}
}
