uint process_event(DeviceInfo info, MYSQL *mysql, int trigger_type, int last_status, int situation, long int last_triggered, string name)
{
MYSQL_RES *mysql_res;
MYSQL_ROW mysql_row;
uint status = 0;
string query = "SELECT `value`, `value_type`, `condition`, `logic_condition` FROM `conditions` WHERE `event_id` = '" + inttostr(info.event_id) + "' ORDER BY `id`";
mysql_res = db_query(mysql, &info, query);
for (uint i = 0; i < mysql_num_rows(mysql_res); i++)
{
mysql_row = mysql_fetch_row(mysql_res);
if (i == 0)
{
status = process_condition(info, strtoint(mysql_row[0]), strtoint(mysql_row[1]), strtoint(mysql_row[2]));
}
else
{
switch (strtoint(mysql_row[3]))
{
case 0: status = status && process_condition(info, strtoint(mysql_row[0]), strtoint(mysql_row[1]), strtoint(mysql_row[2]));
break;
case 1: status = status || process_condition(info, strtoint(mysql_row[0]), strtoint(mysql_row[1]), strtoint(mysql_row[2]));
break;
}
}
}
mysql_free_result(mysql_res);
if (status == 0)
{
debuglogger(DEBUG_EVENT, LEVEL_INFO, &info, "Not Triggered.");
db_update(mysql, &info, "UPDATE events SET last_status=0 WHERE id=" + inttostr(info.event_id));
return 0;
}
else
{
debuglogger(DEBUG_EVENT, LEVEL_INFO, &info, "Triggered.");
// setup parameters for the response to use.
info.parameters.push_front(ValuePair("event_name", name));
info.parameters.push_front(ValuePair("situation", situations[situation]));
if ((uint) last_status != status)
{
db_update(mysql, &info, "UPDATE events SET last_triggered=UNIX_TIMESTAMP(NOW()), last_status=1 WHERE id=" + inttostr(info.event_id));
db_update(mysql, &info, "INSERT INTO event_log SET date=UNIX_TIMESTAMP(NOW()), time_since_last_change=UNIX_TIMESTAMP(NOW())-" + inttostr(last_triggered) + ", event_id=" + inttostr(info.event_id));
process_responses(info, mysql);
}
return 1;
}
} // end process_event()
static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
u8 *buffer, u32 len, u32 iswrite)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct crqb *req;
int slot;
u32 start;
if (len >= 64 * 1024) {
printf("We only support <64K transfers for now\n");
return -1;
}
/* Initialize request */
slot = get_reqip(port);
memset(&priv->request[slot], 0, sizeof(struct crqb));
req = &priv->request[slot];
req->dtb_low = (u32)buffer;
/* Dont use PRDs */
req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
req->control_flags |=
((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
& CRQB_CNTRLFLAGS_PMPORTMASK);
req->drb_count = len;
req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
CRQB_CMDFEAT_CMDMASK;
req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
CRQB_CMDFEAT_FEATMASK;
req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
CRQB_ADDR_LBA_LOWMASK;
req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
CRQB_ADDR_LBA_MIDMASK;
req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
CRQB_ADDR_LBA_HIGHMASK;
req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
CRQB_ADDR_DEVICE_MASK;
req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
CRQB_ADDR_LBA_LOW_EXP_MASK;
req->ata_addr_exp |=
(cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
CRQB_ADDR_LBA_MID_EXP_MASK;
req->ata_addr_exp |=
(cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
CRQB_ADDR_LBA_HIGH_EXP_MASK;
req->ata_addr_exp |=
(cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
CRQB_ADDR_FEATURE_EXP_MASK;
req->ata_sect_count =
(cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
CRQB_SECTCOUNT_COUNT_MASK;
req->ata_sect_count |=
(cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
CRQB_SECTCOUNT_COUNT_EXP_MASK;
/* Flush data */
start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(start,
start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
/* Trigger operation */
slot = get_next_reqip(port);
set_reqip(port, slot);
/* Wait for completion */
if (wait_dma_completion(port, slot, 10000)) {
printf("ATA operation timed out\n");
return -1;
}
process_responses(port);
/* Invalidate data on read */
if (buffer && len) {
start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
invalidate_dcache_range(start,
start + ALIGN(len, ARCH_DMA_MINALIGN));
}
return len;
}