/**
* psc_module_release_from_reset() - Release the module from reset
* @mod_num: LPSC module number
*
* This is the follow through for the command 'psc_module_keep_in_reset_enabled'
* Allowing the module to be released from reset once all required inits are
* complete for the module. Typically, this allows the processor module to start
* execution.
*/
int psc_module_release_from_reset(u32 mod_num)
{
u32 mdctl, mdstat;
int domain_num = psc_get_domain_num(mod_num);
int timeout = 100000;
/* Wait for any previous transitions to complete */
psc_wait(domain_num);
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Should be set to 1 to de-assert Local reset */
if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) {
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Wait for transition to take place */
psc_wait(domain_num);
}
mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
while (timeout) {
mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
break;
timeout--;
}
if (!timeout) {
printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
__func__, mdstat);
return -ETIMEDOUT;
}
return 0;
}
/*
* FUNCTION PURPOSE: Power up/down a module
*
* DESCRIPTION: Powers up/down the requested module and the associated power
* domain if required. No action is taken it the module is
* already powered up/down.
*
* This only controls modules. The domain in which the module
* resides will be left in the power on state. Multiple modules
* can exist in a power domain, so powering down the domain based
* on a single module is not done.
*
* Returns 0 on success, -1 if the module can't be powered up, or
* if there is a timeout waiting for the transition.
*/
int psc_set_state(u32 mod_num, u32 state)
{
u32 domain_num;
u32 pdctl;
u32 mdctl;
u32 ptcmd;
u32 reset_iso;
u32 v;
/*
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
/* Wait for the status of the domain/module to be non-transitional */
if (psc_wait(domain_num) != 0)
return -1;
/*
* Perform configuration even if the current status matches the
* existing state
*
* Set the next state of the power domain to on. It's OK if the domain
* is always on. This code will not ever power down a domain, so no
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
}
/**
* psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state
* @mod_num: LPSC module number
* @gate_clocks: Can the clocks be gated on this module?
*
* Enable the module, but do not release the module from local reset. This is
* necessary for many processor systems on keystone SoCs to allow for system
* initialization from a master processor prior to releasing the processor
* from reset.
*/
int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks)
{
u32 mdctl, ptcmd, mdstat;
u32 next_state;
int domain_num = psc_get_domain_num(mod_num);
int timeout = 100000;
/* Wait for any previous transitions to complete */
psc_wait(domain_num);
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Should be set 0 to assert Local reset */
if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) {
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Wait for transition to take place */
psc_wait(domain_num);
}
/* Clear Module reset */
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF :
PSC_REG_VAL_MDCTL_NEXT_ON;
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Trigger PD transition */
ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
psc_wait(domain_num);
mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
while (timeout) {
mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
break;
timeout--;
}
if (!timeout) {
printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
__func__, mdstat);
return -ETIMEDOUT;
}
return 0;
}
/*
* FUNCTION PURPOSE: Disable a power domain
*
* DESCRIPTION: The power domain is disabled
*/
int psc_disable_domain(u32 domain_num)
{
u32 pdctl;
u32 ptcmd;
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}
/**
* psc_disable_domain() - Disable a power domain
* @domain_num: GPSC domain number
*/
int psc_disable_domain(u32 domain_num)
{
u32 pdctl;
u32 ptcmd;
pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
return psc_wait(domain_num);
}
