static void set_timer(unsigned long timer_value)
{
put_wvalue(TIMECNTL0, (get_wvalue(TIMECNTL0) & 0xFFE7)); // disable interrupt and stop timer0
put_wvalue(TIMECMP1, timer_value); // load the new interval in the compare register
put_wvalue(TIMEBASE0, 0x0000); // initialize the time base of the counter
put_wvalue(TIMECNTL0, (get_wvalue(TIMECNTL0) & 0xFFF7)); // make timer periodic
put_wvalue(TIMECNTL0, (get_wvalue(TIMECNTL0) | 0x0018)); // enable interrupt and start timer0 as one-shot timer
return;
}
//*********************************************************************************************************************
// function : de_fce_set_ce(unsigned int sel, unsigned int chno, unsigned int ce_lut[256])
// description : set ce lut, directly write to registers
// parameters :
// sel <rtmx select>
// chno <overlay select>
// ce_lut[256] <ce lut>
// return :
// success
//*********************************************************************************************************************
int de_fce_set_ce(unsigned int sel, unsigned int chno, unsigned char ce_lut[256])
{
unsigned int base;
base = fce_hw_base[sel][chno];
//set lut to ce_lut SRAM
//memcpy((unsigned char *)fce_dev[sel][chno]->celut[0], (unsigned char *)ce_lut, sizeof(unsigned char)*256);
put_wvalue(base + 0x28, 0x1); //AHB access CE LUT
memcpy((void*)fce_celut_block[sel][chno].off, (unsigned char *)ce_lut, sizeof(unsigned char)*256);
put_wvalue(base + 0x28, 0x0); //Module access CE LUT
return 0;
}
int de_smbl_set_lut(unsigned int sel, unsigned short *lut)
{
unsigned int base, reg_val;
base = smbl_hw_base[sel];
//set lut to smbl lut SRAM
memcpy((void*)smbl_lut_block[sel].off, (unsigned char *)lut, sizeof(unsigned short)*256);
reg_val = get_wvalue(base);
reg_val |= 0x00000010;
put_wvalue(base, reg_val);
return 0;
}
int de_smbl_update_regs(unsigned int sel)
{
unsigned int reg_val;
if(smbl_ctrl_block[sel].dirty == 0x1){
memcpy((void *)smbl_ctrl_block[sel].off,smbl_ctrl_block[sel].val,smbl_ctrl_block[sel].size);
smbl_ctrl_block[sel].dirty = 0x0;
}
if(smbl_enable_block[sel].dirty == 0x1) {
reg_val = get_wvalue(smbl_enable_block[sel].off);
reg_val &= 0x2;
reg_val |= *((volatile u32*)smbl_enable_block[sel].val);
put_wvalue(smbl_enable_block[sel].off, reg_val);
smbl_enable_block[sel].dirty = 0;
}
return 0;
}
/**
* @brief timer hardware routine
*/
void timer_hardware_init(uint8_t interval, uint8_t scale){
HAS_CRITICAL_SECTION;
unsigned long timer_value;
timer_value = ((0x10000L*(16*1000)-((interval)*(CCLK)))/(16*1000));
ENTER_CRITICAL_SECTION();
IRQ_HANDLER_TABLE[INT_TIMER0] = timer0_interrupt_handler;
set_wbit(ILC, ILC_ILC16 & ILC_INT_LV1); /* interrupt level of
|| || IRQ number 16 (timer0) is set as 1
IRQ number interrupt level */
//! Initialize and start hardware timer
set_timer(timer_value);
LEAVE_CRITICAL_SECTION();
// enable timer by writing '1' in TMEN[0] register
put_wvalue(TMEN, 0x01);
//! Call the SOS timer init function
timer_init();
}
static void hdmi_writel(unsigned int addr, unsigned int data)
{
put_wvalue(hdmi_base_addr + addr, data);
}
/**
* @brief real Timer handler
*/
static void timer0_interrupt_handler()
{
_timer_interrupt();
put_wvalue(TIMESTAT0, 0x01); // implicitly clear the STATUS of the timer0
// so that timer interrupts can be re-enabled
}
