static void tosa_gpio_setup(PXA2xxState *cpu,
DeviceState *scp0,
DeviceState *scp1,
TC6393xbState *tmio)
{
qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc,
qdev_get_gpio_in(scp0, TOSA_GPIO_SD_WP),
qemu_irq_invert(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_nSD_DETECT)));
/* Handle reset */
qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, cpu->reset);
/* PCMCIA signals: card's IRQ and Card-Detect */
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_CF_IRQ),
qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_CF_CD));
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_JC_CF_IRQ),
NULL);
qdev_connect_gpio_out(scp1, TOSA_GPIO_BT_LED, outsignals[0]);
qdev_connect_gpio_out(scp1, TOSA_GPIO_NOTE_LED, outsignals[1]);
qdev_connect_gpio_out(scp1, TOSA_GPIO_CHRG_ERR_LED, outsignals[2]);
qdev_connect_gpio_out(scp1, TOSA_GPIO_WLAN_LED, outsignals[3]);
qdev_connect_gpio_out(scp1, TOSA_GPIO_TC6393XB_L3V_ON, tc6393xb_l3v_get(tmio));
/* UDC Vbus */
qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_USB_IN));
}
static int multi_serial_pci_init(PCIDevice *dev)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
SerialState *s;
int i;
switch (pc->device_id) {
case 0x0003:
pci->ports = 2;
break;
case 0x0004:
pci->ports = 4;
break;
}
assert(pci->ports > 0);
assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
memory_region_init(&pci->iobar, "multiserial", 8 * pci->ports);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
pci->ports);
for (i = 0; i < pci->ports; i++) {
s = pci->state + i;
s->baudbase = 115200;
serial_init_core(s);
s->irq = pci->irqs[i];
pci->name[i] = g_strdup_printf("uart #%d", i+1);
memory_region_init_io(&s->io, &serial_io_ops, s, pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
}
return 0;
}
qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
{
qemu_irq *s = g_malloc0(2 * sizeof(qemu_irq));
s[0] = irq1;
s[1] = irq2;
return qemu_allocate_irqs(qemu_splitirq, s, 1)[0];
}
qemu_irq *kvm_i8259_init(ISABus *bus)
{
i8259_init_chip("kvm-i8259", bus, true);
i8259_init_chip("kvm-i8259", bus, false);
return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS);
}
qemu_irq *i8259_init(qemu_irq parent_irq)
/* We ignore the parent irq entirely. The parent irq is attached to
* hw/pc.c:pic_irq_request
*/
{
return qemu_allocate_irqs(i8259_set_irq, 0, 16);
}
static void palmte_gpio_setup(struct omap_mpu_state_s *cpu)
{
qemu_irq *misc_gpio;
omap_mmc_handlers(cpu->mmc,
qdev_get_gpio_in(cpu->gpio, PALMTE_MMC_WP_GPIO),
qemu_irq_invert(omap_mpuio_in_get(cpu->mpuio)
[PALMTE_MMC_SWITCH_GPIO]));
misc_gpio = qemu_allocate_irqs(palmte_onoff_gpios, cpu, 7);
qdev_connect_gpio_out(cpu->gpio, PALMTE_MMC_POWER_GPIO, misc_gpio[0]);
qdev_connect_gpio_out(cpu->gpio, PALMTE_SPEAKER_GPIO, misc_gpio[1]);
qdev_connect_gpio_out(cpu->gpio, 11, misc_gpio[2]);
qdev_connect_gpio_out(cpu->gpio, 12, misc_gpio[3]);
qdev_connect_gpio_out(cpu->gpio, 13, misc_gpio[4]);
omap_mpuio_out_set(cpu->mpuio, 1, misc_gpio[5]);
omap_mpuio_out_set(cpu->mpuio, 3, misc_gpio[6]);
/* Reset some inputs to initial state. */
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, PALMTE_USBDETECT_GPIO));
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, PALMTE_USB_OR_DC_GPIO));
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, 4));
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, PALMTE_HEADPHONES_GPIO));
qemu_irq_lower(omap_mpuio_in_get(cpu->mpuio)[PALMTE_DC_GPIO]);
qemu_irq_raise(omap_mpuio_in_get(cpu->mpuio)[6]);
qemu_irq_raise(omap_mpuio_in_get(cpu->mpuio)[7]);
qemu_irq_raise(omap_mpuio_in_get(cpu->mpuio)[11]);
}
static void puv3_soc_init(CPUUniCore32State *env)
{
qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
DeviceState *dev;
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
int i;
/* Initialize interrupt controller */
cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
}
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
irqs[PUV3_IRQS_GPIOHIGH], NULL);
/* Keyboard (i8042), mouse disabled for nographic */
i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
}
static void tosa_gpio_setup(PXA2xxState *cpu,
ScoopInfo *scp0,
ScoopInfo *scp1,
TC6393xbState *tmio)
{
qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc,
scoop_gpio_in_get(scp0)[TOSA_GPIO_SD_WP],
qemu_irq_invert(pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_nSD_DETECT]));
/* Handle reset */
pxa2xx_gpio_out_set(cpu->gpio, TOSA_GPIO_ON_RESET, cpu->reset);
/* PCMCIA signals: card's IRQ and Card-Detect */
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_CF_IRQ],
pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_CF_CD]);
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_JC_CF_IRQ],
NULL);
scoop_gpio_out_set(scp1, TOSA_GPIO_BT_LED, outsignals[0]);
scoop_gpio_out_set(scp1, TOSA_GPIO_NOTE_LED, outsignals[1]);
scoop_gpio_out_set(scp1, TOSA_GPIO_CHRG_ERR_LED, outsignals[2]);
scoop_gpio_out_set(scp1, TOSA_GPIO_WLAN_LED, outsignals[3]);
scoop_gpio_out_set(scp1, TOSA_GPIO_TC6393XB_L3V_ON, tc6393xb_l3v_get(tmio));
}
static void cpu_devinit(const char *cpu_model, unsigned int id,
uint64_t prom_addr, qemu_irq **cpu_irqs)
{
CPUState *cs;
SPARCCPU *cpu;
CPUSPARCState *env;
cpu = cpu_sparc_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);
}
env = &cpu->env;
cpu_sparc_set_id(env, id);
if (id == 0) {
qemu_register_reset(main_cpu_reset, cpu);
} else {
qemu_register_reset(secondary_cpu_reset, cpu);
cs = CPU(cpu);
cs->halted = 1;
}
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
env->prom_addr = prom_addr;
}
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
{
Error *local_err = NULL;
ISABus *isa_bus;
qemu_irq *irqs;
qemu_irq_handler handler;
/* let isa_bus_new() create its own bridge on SysBus otherwise
* devices speficied on the command line won't find the bus and
* will fail to create.
*/
isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return NULL;
}
/* Not all variants have a working serial irq decoder. If not,
* handling of LPC interrupts becomes a platform issue (some
* platforms have a CPLD to do it).
*/
if (use_cpld) {
handler = pnv_lpc_isa_irq_handler_cpld;
} else {
handler = pnv_lpc_isa_irq_handler;
}
irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
isa_bus_irqs(isa_bus, irqs);
return isa_bus;
}
void *esp_init(target_phys_addr_t espaddr, int it_shift,
espdma_memory_read_write dma_memory_read,
espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
ESPState *s;
int esp_io_memory;
s = qemu_mallocz(sizeof(ESPState));
if (!s)
return NULL;
s->irq = irq;
s->it_shift = it_shift;
s->dma_memory_read = dma_memory_read;
s->dma_memory_write = dma_memory_write;
s->dma_opaque = dma_opaque;
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory);
esp_reset(s);
register_savevm("esp", espaddr, 3, esp_save, esp_load, s);
qemu_register_reset(esp_reset, s);
*reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
return s;
}
qemu_irq* goldfish_interrupt_init(uint32_t base, qemu_irq parent_irq, qemu_irq parent_fiq)
{
int ret;
struct goldfish_int_state *s;
qemu_irq* qi;
s = qemu_mallocz(sizeof(*s));
qi = qemu_allocate_irqs(goldfish_int_set_irq, s, GFD_MAX_IRQ);
s->dev.name = "goldfish_interrupt_controller";
s->dev.id = -1;
s->dev.base = base;
s->dev.size = 0x1000;
s->parent_irq = parent_irq;
s->parent_fiq = parent_fiq;
ret = goldfish_device_add(&s->dev, goldfish_int_readfn, goldfish_int_writefn, s);
if(ret) {
qemu_free(s);
return NULL;
}
register_savevm( "goldfish_int", 0, GOLDFISH_INT_SAVE_VERSION,
goldfish_int_save, goldfish_int_load, s);
return qi;
}
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
{
int iomemtype;
PXA2xxPCMCIAState *s;
s = (PXA2xxPCMCIAState *)
qemu_mallocz(sizeof(PXA2xxPCMCIAState));
/* Socket I/O Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
pxa2xx_pcmcia_io_writefn, s);
cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
pxa2xx_pcmcia_attr_writefn, s);
cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
/* Socket Common Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
pxa2xx_pcmcia_common_writefn, s);
cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
if (base == 0x30000000)
s->slot.slot_string = "PXA PC Card Socket 1";
else
s->slot.slot_string = "PXA PC Card Socket 0";
s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0];
pcmcia_socket_register(&s->slot);
return s;
}
/* EBUS (Eight bit bus) bridge */
static void
pci_ebus_init(PCIBus *bus, int devfn)
{
qemu_irq *isa_irq;
pci_create_simple(bus, devfn, "ebus");
isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
isa_bus_irqs(isa_irq);
}
TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
{
TC6393xbState *s;
DriveInfo *nand;
static const MemoryRegionOps tc6393xb_ops = {
.read = tc6393xb_readb,
.write = tc6393xb_writeb,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
};
s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
s->irq = irq;
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
s->blanked = 1;
s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
nand = drive_get(IF_MTD, 0, 0);
s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
memory_region_add_subregion(sysmem, base, &s->iomem);
memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
vmstate_register_ram_global(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
s->scr_width = 480;
s->scr_height = 640;
s->con = graphic_console_init(tc6393xb_update_display,
NULL, /* invalidate */
NULL, /* screen_dump */
NULL, /* text_update */
s);
return s;
}
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
{
int i;
qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
for (i = 0; i < n; i++) {
*old_irqs[i] = *gpio_in[i];
gpio_in[i]->handler = handler;
gpio_in[i]->opaque = old_irqs;
}
}
void cpu_riscv_irq_init_cpu(CPURISCVState *env)
{
qemu_irq *qi;
int i;
qi = qemu_allocate_irqs(cpu_riscv_irq_request, riscv_env_get_cpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
}
void cpu_mips_irq_init_cpu(CPUOldState *env)
{
qemu_irq *qi;
int i;
qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
}
static void ics_realize(DeviceState *dev, Error **errp)
{
ICSState *ics = ICS(dev);
if (!ics->nr_irqs) {
error_setg(errp, "Number of interrupts needs to be greater 0");
return;
}
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
}
void xtensa_irq_init(CPUXtensaState *env)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
env->irq_inputs = (void **)qemu_allocate_irqs(
xtensa_set_irq, env, env->config->ninterrupt);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
env->config->nccompare > 0) {
env->ccompare_timer =
qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, cpu);
}
}
void cpu_mips_irq_init_cpu(CPUMIPSState *env)
{
#if 0
qemu_irq *qi;
int i;
qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
#endif
}
TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
{
TC6393xbState *s;
DriveInfo *nand;
static const MemoryRegionOps tc6393xb_ops = {
.read = tc6393xb_readb,
.write = tc6393xb_writeb,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
};
s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
s->irq = irq;
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
s->blanked = 1;
s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
nand = drive_get(IF_MTD, 0, 0);
s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
NAND_MFR_TOSHIBA, 0x76);
memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
memory_region_add_subregion(sysmem, base, &s->iomem);
memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
&error_fatal);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
s->scr_width = 480;
s->scr_height = 640;
s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);
return s;
}
/* EBUS (Eight bit bus) bridge */
static ISABus *
pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
{
qemu_irq *isa_irq;
PCIDevice *pci_dev;
ISABus *isa_bus;
pci_dev = pci_create_simple(bus, devfn, "ebus");
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
isa_bus_irqs(isa_bus, isa_irq);
return isa_bus;
}
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
hwaddr base, qemu_irq irl)
{
r2d_fpga_t *s;
s = g_malloc0(sizeof(r2d_fpga_t));
s->irl = irl;
memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}
/* EBUS (Eight bit bus) bridge */
static ISABus *
pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
{
qemu_irq *isa_irq;
PCIDevice *pci_dev;
ISABus *isa_bus;
pci_dev = pci_create_simple(bus, devfn, "ebus");
isa_bus = DO_UPCAST(ISABus, qbus,
qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
isa_bus_irqs(isa_bus, isa_irq);
return isa_bus;
}
static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
{
int iomemtype;
r2d_fpga_t *s;
s = qemu_mallocz(sizeof(r2d_fpga_t));
s->irl = irl;
iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
r2d_fpga_writefn, s);
cpu_register_physical_memory(base, 0x40, iomemtype);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}
static void fdt_init_all_irqs(FDTMachineInfo *fdti)
{
while (fdti->irqs) {
FDTIRQConnection *first = fdti->irqs;
qemu_irq sink = first->irq;
bool (*merge_fn)(bool *, int) = first->merge_fn;
int num_sources = 0;
FDTIRQConnection *irq;
for (irq = first; irq; irq = irq->next) {
if (irq->irq == sink) { /* Same sink */
num_sources++;
}
}
if (num_sources > 1) {
QEMUIRQSharedState *s = g_malloc0(sizeof *s);
s->sink = sink;
s->merge_fn = merge_fn;
qemu_irq *sources = qemu_allocate_irqs(qemu_irq_shared_handler, s,
num_sources);
for (irq = first; irq; irq = irq->next) {
if (irq->irq == sink) {
char *shared_irq_name = g_strdup_printf("shared-irq-%p",
*sources);
if (irq->merge_fn != merge_fn) {
fprintf(stderr, "ERROR: inconsistent IRQ merge fns\n");
exit(1);
}
object_property_add_child(OBJECT(irq->dev), shared_irq_name,
OBJECT(*sources), &error_abort);
g_free(shared_irq_name);
irq->irq = *(sources++);
s->num++;
}
}
}
DB_PRINT(0, "%s: connected to %s irq line %d (%s)\n",
first->sink_info ? first->sink_info : "",
object_get_canonical_path(OBJECT(first->dev)),
first->i, first->name ? first->name : "");
qdev_connect_gpio_out_named(DEVICE(first->dev), first->name, first->i,
first->irq);
fdti->irqs = first->next;
g_free(first);
}
}
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
qemu_irq **parent_irq)
{
unsigned int i;
int sbi_io_memory;
SBIState *s;
s = qemu_mallocz(sizeof(SBIState));
for (i = 0; i < MAX_CPUS; i++) {
s->cpu_irqs[i] = parent_irq[i];
}
sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
qemu_register_reset(sbi_reset, s);
*irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
sbi_reset(s);
return s;
}
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
hwaddr base,
M68kCPU *cpu)
{
mcf_intc_state *s;
s = g_malloc0(sizeof(mcf_intc_state));
s->cpu = cpu;
mcf_intc_reset(s);
memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
}
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
{
mcf_intc_state *s;
int iomemtype;
s = qemu_mallocz(sizeof(mcf_intc_state));
s->env = env;
mcf_intc_reset(s);
iomemtype = cpu_register_io_memory(0, mcf_intc_readfn,
mcf_intc_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
}