void icp_set_cppr(ICPState *icp, uint8_t cppr)
{
uint8_t old_cppr;
uint32_t old_xisr;
old_cppr = CPPR(icp);
icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
if (cppr < old_cppr) {
if (XISR(icp) && (cppr <= icp->pending_priority)) {
old_xisr = XISR(icp);
icp->xirr &= ~XISR_MASK; /* Clear XISR */
icp->pending_priority = 0xff;
qemu_irq_lower(icp->output);
if (icp->xirr_owner) {
ics_reject(icp->xirr_owner, old_xisr);
icp->xirr_owner = NULL;
}
}
} else {
if (!XISR(icp)) {
icp_resend(icp);
}
}
}
static void puv3_ost_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3OSTState *s = opaque;
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
switch (offset) {
case 0x00: /* Match Register 0 */
s->reg_OSMR0 = value;
if (s->reg_OSMR0 > s->reg_OSCR) {
ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
} else {
ptimer_set_count(s->ptimer, s->reg_OSMR0 +
(0xffffffff - s->reg_OSCR));
}
ptimer_run(s->ptimer, 2);
break;
case 0x14: /* Status Register */
assert(value == 0);
if (s->reg_OSSR) {
s->reg_OSSR = value;
qemu_irq_lower(s->irq);
}
break;
case 0x1c: /* Interrupt Enable Register */
s->reg_OIER = value;
break;
default:
DPRINTF("Bad offset %x\n", (int)offset);
}
}
static void parallel_update_irq(ParallelState *s)
{
if (s->irq_pending)
qemu_irq_raise(s->irq);
else
qemu_irq_lower(s->irq);
}
void musb_core_intr_clear(MUSBState *s, uint32_t mask)
{
if (s->rx_intr) {
s->rx_intr &= mask >> 15;
if (!s->rx_intr)
qemu_irq_lower(s->irqs[musb_irq_rx]);
}
static void sun4c_check_interrupts(void *opaque)
{
Sun4c_INTCTLState *s = opaque;
uint32_t pil_pending;
unsigned int i;
pil_pending = 0;
if (s->pending && !(s->reg & 0x80000000)) {
for (i = 0; i < 8; i++) {
if (s->pending & (1 << i))
pil_pending |= 1 << intbit_to_level[i];
}
}
for (i = 0; i < MAX_PILS; i++) {
if (pil_pending & (1 << i)) {
if (!(s->pil_out & (1 << i)))
qemu_irq_raise(s->cpu_irqs[i]);
} else {
if (s->pil_out & (1 << i))
qemu_irq_lower(s->cpu_irqs[i]);
}
}
s->pil_out = pil_pending;
}
static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq)
{
IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
IPMIBT *ib = iic->get_backend_data(ii);
if (!!val == IPMI_BT_GET_SMS_ATN(ib->control_reg)) {
return;
}
IPMI_BT_SET_SMS_ATN(ib->control_reg, val);
if (val) {
if (irq && ib->use_irq && ib->irqs_enabled &&
!IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
qemu_irq_raise(ib->irq);
}
} else {
if (!IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
qemu_irq_lower(ib->irq);
}
}
}
static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
uint32_t tmp;
switch (offset) {
case KPC:
tmp = s->kpc;
if(tmp & KPC_MI)
s->kpc &= ~(KPC_MI);
if(tmp & KPC_DI)
s->kpc &= ~(KPC_DI);
qemu_irq_lower(s->irq);
return tmp;
break;
case KPDK:
return s->kpdk;
break;
case KPREC:
tmp = s->kprec;
if(tmp & KPREC_OF1)
s->kprec &= ~(KPREC_OF1);
if(tmp & KPREC_UF1)
s->kprec &= ~(KPREC_UF1);
if(tmp & KPREC_OF0)
s->kprec &= ~(KPREC_OF0);
if(tmp & KPREC_UF0)
s->kprec &= ~(KPREC_UF0);
return tmp;
break;
case KPMK:
tmp = s->kpmk;
if(tmp & KPMK_MKP)
s->kpmk &= ~(KPMK_MKP);
return tmp;
break;
case KPAS:
return s->kpas;
break;
case KPASMKP0:
return s->kpasmkp[0];
break;
case KPASMKP1:
return s->kpasmkp[1];
break;
case KPASMKP2:
return s->kpasmkp[2];
break;
case KPASMKP3:
return s->kpasmkp[3];
break;
case KPKDI:
return s->kpkdi;
break;
default:
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
}
static void esp_lower_irq(ESPState *s)
{
if (s->rregs[ESP_RSTAT] & STAT_INT) {
s->rregs[ESP_RSTAT] &= ~STAT_INT;
qemu_irq_lower(s->irq);
}
}
static void esp_soft_reset(DeviceState *d)
{
ESPState *s = container_of(d, ESPState, busdev.qdev);
qemu_irq_lower(s->irq);
esp_hard_reset(d);
}
static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
{
unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
unsigned int wd_key = t->rw_wd_ctrl >> 9;
unsigned int wd_cnt = t->rw_wd_ctrl & 511;
unsigned int new_key = value >> 9 & ((1 << 7) - 1);
unsigned int new_cmd = (value >> 8) & 1;
/* If the watchdog is enabled, they written key must match the
complement of the previous. */
wd_key = ~wd_key & ((1 << 7) - 1);
if (wd_en && wd_key != new_key)
return;
D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
wd_en, new_key, wd_key, new_cmd, wd_cnt));
if (t->wd_hits)
qemu_irq_lower(t->nmi);
t->wd_hits = 0;
ptimer_set_freq(t->ptimer_wd, 760);
if (wd_cnt == 0)
wd_cnt = 256;
ptimer_set_count(t->ptimer_wd, wd_cnt);
if (new_cmd)
ptimer_run(t->ptimer_wd, 1);
else
ptimer_stop(t->ptimer_wd);
t->rw_wd_ctrl = value;
}
static void s5l8930_spi_mm_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
S5L8930SPIState *s = (S5L8930SPIState *)opaque;
fprintf(stderr, "%s: base 0x%08x offset 0x%08x value 0x%08x\n", __func__, s->base, offset, val);
switch (offset) {
case SPI_CONTROL:
if(val & 0x1) {
if(s->setup & 0x200000) {
// tx
s->status = 0x400002;
s->cmd = s->tx_data[0];
pflash_cmd_set(s->pflash, s->tx_data);
//fprintf(stderr, "%s: base: %d txCmd: %d\n", __FUNCTION__, s->base, s->cmd);
} else {
// rx
s->rxFifoCnt = 0;
s->status |= 1;
s->status |= pflash_cmd_len(s->pflash) << 11;
//fprintf(stderr, "%s: base: %d rxBuf: %d\n", __FUNCTION__, s->base, RX_BUFFER_LEFT(s->status));
}
qemu_irq_raise(s->irq);
}
break;
case SPI_SETUP:
s->setup = val;
break;
case SPI_STATUS:
//fprintf(stderr, "%s: clearing irq on base %d\n", __FUNCTION__, s->base);
qemu_irq_lower(s->irq);
s->status = 0;
s->txBuffer = 0;
break;
case SPI_PIN:
s->pin = val;
break;
case SPI_TXDATA:
s->tx_data[s->txBuffer++] = val;
break;
case SPI_RXDATA:
s->rx_data = val;
break;
case SPI_CLKDIV:
s->clkdiv = val;
break;
case SPI_CNT:
pflash_set_rxlen(s->pflash, val);
s->cnt = val;
break;
case SPI_IDD:
s->idd = val;
break;
default:
fprintf(stderr, "%s: BAD Write base 0x%08x offset 0x%08x value 0x%08x\n", __func__, s->base, offset, val);
//hw_error("s5l8930_spi: bad write offset 0x" TARGET_FMT_plx "\n", offset);
}
}
static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
TimerContext *tc = opaque;
SLAVIO_TIMERState *s = tc->s;
uint32_t saddr, ret;
unsigned int timer_index = tc->timer_index;
CPUTimerState *t = &s->cputimer[timer_index];
saddr = addr >> 2;
switch (saddr) {
case TIMER_LIMIT:
// read limit (system counter mode) or read most signifying
// part of counter (user mode)
if (slavio_timer_is_user(tc)) {
// read user timer MSW
slavio_timer_get_out(t);
ret = t->counthigh | t->reached;
} else {
// read limit
// clear irq
qemu_irq_lower(t->irq);
t->reached = 0;
ret = t->limit & TIMER_LIMIT_MASK32;
}
break;
case TIMER_COUNTER:
// read counter and reached bit (system mode) or read lsbits
// of counter (user mode)
slavio_timer_get_out(t);
if (slavio_timer_is_user(tc)) { // read user timer LSW
ret = t->count & TIMER_MAX_COUNT64;
} else { // read limit
ret = (t->count & TIMER_MAX_COUNT32) |
t->reached;
}
break;
case TIMER_STATUS:
// only available in processor counter/timer
// read start/stop status
if (timer_index > 0) {
ret = t->run;
} else {
ret = 0;
}
break;
case TIMER_MODE:
// only available in system counter
// read user/system mode
ret = s->cputimer_mode;
break;
default:
trace_slavio_timer_mem_readl_invalid(addr);
ret = 0;
break;
}
trace_slavio_timer_mem_readl(addr, ret);
return ret;
}
/*
* Update interrupt status
*/
static void imx_epit_update_int(IMXEPITState *s)
{
if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
static void imx_gpt_update_int(IMXGPTState *s)
{
if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
/* Update interrupt status after enabled or pending bits have been changed. */
static void puv3_intc_update(PUV3INTCState *s)
{
if (s->reg_ICMR & s->reg_ICPR) {
qemu_irq_raise(s->parent_irq);
} else {
qemu_irq_lower(s->parent_irq);
}
}
static uint32_t sio_data_read(void *opaque, uint32_t addr)
{
KeyBoardState *s = opaque;
s->status &= ~SIO_STAT_RXRDY;
qemu_irq_lower(s->pic);
return s->recv_data;
}
static uint32_t icp_accept(struct icp_server_state *ss)
{
uint32_t xirr;
qemu_irq_lower(ss->output);
xirr = ss->xirr;
ss->xirr = ss->pending_priority << 24;
return xirr;
}
static void arm_timer_update(arm_timer_state *s)
{
/* Update interrupts. */
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
static uint32_t s5l8930_spi_mm_read(void *opaque, target_phys_addr_t offset)
{
S5L8930SPIState *s = (S5L8930SPIState *)opaque;
// fprintf(stderr, "%s: base 0x%08x offset 0x%08x\n", __func__, s->base, offset);
switch (offset) {
case SPI_CONTROL:
return s->ctrl;
case SPI_SETUP:
return s->setup;
case SPI_STATUS:
/* Strange that on fifo empty irq handler doesnt clear irq */
qemu_irq_lower(s->irq);
return s->status;
case SPI_PIN:
return s->pin;
case SPI_TXDATA:
return s->tx_data[0];
case SPI_RXDATA:
s->rx_data = pflash_cmd_parse(s->pflash);
s->status |= pflash_cmd_len(s->pflash) << 11;
//fprintf(stderr, "%s: rxBuf 0x%08x\n", __func__, s->rx_data);
/* Queue fifo empty irq */
if(s->rxFifoCnt == 0x1e) {
qemu_irq_lower(s->irq);
qemu_mod_timer(s->timer, qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
} else
s->rxFifoCnt++;
return s->rx_data;
case SPI_CLKDIV:
return s->clkdiv;
case SPI_CNT:
return s->cnt;
case SPI_IDD:
return s->idd;
default:
;
//fprintf(stderr, "%s: base 0x%08x offset 0x%08x\n", __func__, s->base, offset);
//hw_error("s5l8930_spi: bad read offset 0x" TARGET_FMT_plx "\n", offset);
}
return 0;
}
static void pl192_lower(pl192_state *s, int is_fiq)
{
/* Lower parrent interrupt if there is one */
if (is_fiq && s->fiq) {
qemu_irq_lower(s->fiq);
}
if (!is_fiq && s->irq) {
qemu_irq_lower(s->irq);
}
/* Propagate to the previous controller in chain if needed */
if (s->daisy) {
if (!is_fiq) {
s->daisy->daisy_input = 0;
pl192_update(s->daisy);
} else {
pl192_lower(s->daisy, is_fiq);
}
}
}
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
{
AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
DPRINTF(0, "lower irq\n");
if (!msi_enabled(PCI_DEVICE(d))) {
qemu_irq_lower(s->irq);
}
}
/* Eject card from the slot */
int pxa2xx_pcmcia_dettach(void *opaque)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
if (!s->slot.attached)
return -ENOENT;
s->card->detach(s->card->state);
s->card->slot = NULL;
s->card = NULL;
s->slot.attached = 0;
if (s->irq)
qemu_irq_lower(s->irq);
if (s->cd_irq)
qemu_irq_lower(s->cd_irq);
return 0;
}
static void musb_intr_set(MUSBState *s, int line, int level)
{
if (!level) {
s->intr &= ~(1 << line);
qemu_irq_lower(s->irqs[line]);
} else if (s->mask & (1 << line)) {
s->intr |= 1 << line;
qemu_irq_raise(s->irqs[line]);
}
}
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
{
struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
DPRINTF(0, "lower irq\n");
if (!msi_enabled(&d->card)) {
qemu_irq_lower(s->irq);
}
}
static void musb_tx_intr_set(struct musb_s *s, int line, int level)
{
if (!level) {
s->tx_intr &= ~(1 << line);
if (!s->tx_intr)
qemu_irq_lower(s->irqs[musb_irq_tx]);
} else if (s->tx_mask & (1 << line)) {
s->tx_intr |= 1 << line;
qemu_irq_raise(s->irqs[musb_irq_tx]);
}
}
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
{
DeviceState *dev_state = s->container;
PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
TYPE_PCI_DEVICE);
DPRINTF(0, "lower irq\n");
if (!pci_dev || !msi_enabled(pci_dev)) {
qemu_irq_lower(s->irq);
}
}
static uint32_t icp_accept(ICPState *ss)
{
uint32_t xirr = ss->xirr;
qemu_irq_lower(ss->output);
ss->xirr = ss->pending_priority << 24;
ss->pending_priority = 0xff;
trace_xics_icp_accept(xirr, ss->xirr);
return xirr;
}
static void slavio_misc_update_irq(void *opaque)
{
MiscState *s = opaque;
if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
trace_slavio_misc_update_irq_raise();
qemu_irq_raise(s->irq);
} else {
trace_slavio_misc_update_irq_lower();
qemu_irq_lower(s->irq);
}
}
static void update_irq(LM32PicState *s)
{
s->ip |= s->irq_state;
if (s->ip & s->im) {
trace_lm32_pic_raise_irq();
qemu_irq_raise(s->parent_irq);
} else {
trace_lm32_pic_lower_irq();
qemu_irq_lower(s->parent_irq);
}
}
static void etraxfs_timer_reset(void *opaque)
{
struct etrax_timer *t = opaque;
ptimer_stop(t->ptimer_t0);
ptimer_stop(t->ptimer_t1);
ptimer_stop(t->ptimer_wd);
t->rw_wd_ctrl = 0;
t->r_intr = 0;
t->rw_intr_mask = 0;
qemu_irq_lower(t->irq);
}
