static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; switch(addr) { case 0x00: { int64_t d; int pmsts; pmsts = get_pmsts(s); if (pmsts & val & TMROF_EN) { /* if TMRSTS is reset, then compute the new overflow time */ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; pm_update_sci(s); } break; case 0x02: s->pmen = val; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, val & RTC_EN); qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, val & TMROF_EN); pm_update_sci(s); break; case 0x04: { int sus_typ; s->pmcntrl = val & ~(SUS_EN); if (val & SUS_EN) { /* change suspend type */ sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: qemu_system_suspend_request(); break; default: if (sus_typ == s->s4_val) { /* S4 request */ monitor_protocol_event(QEVENT_SUSPEND_DISK, NULL); qemu_system_shutdown_request(); } break; } } } break; default: break; }
bool replay_next_event_is(int event) { bool res = false; /* nothing to skip - not all instructions used */ if (replay_state.instructions_count != 0) { assert(replay_state.data_kind == EVENT_INSTRUCTION); return event == EVENT_INSTRUCTION; } while (true) { if (event == replay_state.data_kind) { res = true; } switch (replay_state.data_kind) { case EVENT_SHUTDOWN: replay_finish_event(); qemu_system_shutdown_request(); break; default: /* clock, time_t, checkpoint and other events */ return res; } } return res; }
static void sys_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { LM32SysState *s = opaque; char *testname; trace_lm32_sys_memory_write(addr, value); addr >>= 2; switch (addr) { case R_CTRL: qemu_system_shutdown_request(); break; case R_PASSFAIL: s->regs[addr] = value; testname = (char *)s->testname; qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK"); break; case R_TESTNAME: s->regs[addr] = value; copy_testname(s); break; default: error_report("lm32_sys: write access to unknown register 0x" TARGET_FMT_plx, addr << 2); break; } }
static void sys_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { LM32SysState *s = opaque; char *testname; trace_lm32_sys_memory_write(addr, value); addr >>= 2; switch (addr) { case R_CTRL: qemu_system_shutdown_request(); break; case R_PASSFAIL: s->regs[addr] = value; testname = (char *)s->testname; fprintf(stderr, "TC %-*s %s\n", MAX_TESTNAME_LEN, testname, (value) ? "FAILED" : "OK"); if (value) { cpu_dump_state(qemu_get_cpu(0), stderr, fprintf, 0); } break; case R_TESTNAME: s->regs[addr] = value; copy_testname(s); break; default: error_report("lm32_sys: write access to unknown register 0x" TARGET_FMT_plx, addr << 2); break; } }
/* Power */ static void power_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { /* According to a real Ultra 5, bit 24 controls the power */ if (val & 0x1000000) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } }
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, uint32_t val) { if ((addr & 0xffff) == 0 && val == 42) qemu_system_reset_request (); else if ((addr & 0xffff) == 4 && val == 42) qemu_system_shutdown_request (); }
static void mips_qemu_write (void *opaque, hwaddr addr, uint64_t val, unsigned size) { if ((addr & 0xffff) == 0 && val == 42) qemu_system_reset_request (); else if ((addr & 0xffff) == 4 && val == 42) qemu_system_shutdown_request (); }
static void mips_qemu_write (void *opaque, hwaddr addr, uint64_t val, unsigned size) { if ((addr & 0xffff) == 0 && val == 42) qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); else if ((addr & 0xffff) == 4 && val == 42) qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); }
static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value) { trace_milkymist_sysctl_icap_write(value); switch (value & 0xffff) { case 0x000e: qemu_system_shutdown_request(); break; } }
static void rtas_power_off(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { if (nargs != 2 || nret != 1) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); return; } qemu_system_shutdown_request(); rtas_st(rets, 0, RTAS_OUT_SUCCESS); }
void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val, char s4) { ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE); if (val & ACPI_BITMASK_SLEEP_ENABLE) { /* change suspend type */ uint16_t sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: qemu_system_suspend_request(); break; default: if (sus_typ == s4) { /* S4 request */ qemu_system_shutdown_request(); } break; } }
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; switch(addr) { case 0x00: { int64_t d; int pmsts; pmsts = get_pmsts(s); if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) { /* if TMRSTS is reset, then compute the new overflow time */ d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; pm_update_sci(s); } break; case 0x02: s->pmen = val; pm_update_sci(s); break; case 0x04: { int sus_typ; s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE); if (val & ACPI_BITMASK_SLEEP_ENABLE) { /* change suspend type */ sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: /* ACPI_BITMASK_WAKE_STATUS should be set on resume. Pretend that resume was caused by power button */ s->pmsts |= (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS); qemu_system_reset_request(); if (s->cmos_s3) { qemu_irq_raise(s->cmos_s3); } default: break; } } } break; default: break; }
static void rtas_power_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { if (nargs != 2 || nret != 1) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); return; } qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); cpu_stop_current(); rtas_st(rets, 0, RTAS_OUT_SUCCESS); }
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; switch(addr) { case 0x00: { int64_t d; int pmsts; pmsts = get_pmsts(s); if (pmsts & val & TMROF_EN) { /* if TMRSTS is reset, then compute the new overflow time */ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; pm_update_sci(s); } break; case 0x02: s->pmen = val; pm_update_sci(s); break; case 0x04: { int sus_typ; s->pmcntrl = val & ~(SUS_EN); if (val & SUS_EN) { /* change suspend type */ sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: /* RSM_STS should be set on resume. Pretend that resume was caused by power button */ s->pmsts |= (RSM_STS | PWRBTN_STS); qemu_system_reset_request(); #if defined(TARGET_I386) cmos_set_s3_resume(); #endif default: break; } } } break; default: break; }
/* ACPI PM1aCNT */ static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val) { ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE); if (val & ACPI_BITMASK_SLEEP_ENABLE) { /* change suspend type */ uint16_t sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: qemu_system_suspend_request(); break; default: if (sus_typ == ar->pm1.cnt.s4_val) { /* S4 request */ monitor_protocol_event(QEVENT_SUSPEND_DISK, NULL); qemu_system_shutdown_request(); } break; } }
/* ACPI PM1aCNT */ static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val) { ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE); if (val & ACPI_BITMASK_SLEEP_ENABLE) { /* change suspend type */ uint16_t sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); break; case 1: qemu_system_suspend_request(); break; default: if (sus_typ == ar->pm1.cnt.s4_val) { /* S4 request */ qapi_event_send_suspend_disk(); qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } break; } }
/* called periodically to poll for user input events */ static void emulator_window_refresh(EmulatorWindow* emulator) { /* this will eventually call sdl_update if the content of the VGA framebuffer * has changed */ qframebuffer_check_updates(); if (emulator->ui) { if (skin_ui_process_events(emulator->ui)) { // Quit program. skin_ui_free(emulator->ui); emulator->ui = NULL; qemu_system_shutdown_request(); } } }
static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr, uint64_t val, unsigned size) { MiscState *s = opaque; val &= AUX2_PWRINTCLR | AUX2_PWROFF; trace_slavio_aux2_mem_writeb(val & 0xff); val |= s->aux2 & AUX2_PWRFAIL; if (val & AUX2_PWRINTCLR) // Clear Power Fail int val &= AUX2_PWROFF; s->aux2 = val; if (val & AUX2_PWROFF) qemu_system_shutdown_request(); slavio_misc_update_irq(s); }
static void hb_regs_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { uint32_t *regs = opaque; if (offset == 0xf00) { if (value == 1 || value == 2) { qemu_system_reset_request(); } else if (value == 3) { qemu_system_shutdown_request(); } } regs[offset/4] = value; }
void s390_handle_wait(S390CPU *cpu) { CPUState *cs = CPU(cpu); if (s390_cpu_halt(cpu) == 0) { #ifndef CONFIG_USER_ONLY if (is_special_wait_psw(cpu->env.psw.addr)) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } else { cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT; qemu_system_guest_panicked(cpu_get_crash_info(cs)); } #endif } }
static void handle_hw_op(IPMIBmcExtern *ibe, unsigned char hw_op) { IPMIInterface *s = ibe->parent.intf; IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s); switch (hw_op) { case VM_CMD_VERSION: /* We only support one version at this time. */ break; case VM_CMD_NOATTN: k->set_atn(s, 0, 0); break; case VM_CMD_ATTN: k->set_atn(s, 1, 0); break; case VM_CMD_ATTN_IRQ: k->set_atn(s, 1, 1); break; case VM_CMD_POWEROFF: k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0); break; case VM_CMD_RESET: k->do_hw_op(s, IPMI_RESET_CHASSIS, 0); break; case VM_CMD_ENABLE_IRQ: k->set_irq_enable(s, 1); break; case VM_CMD_DISABLE_IRQ: k->set_irq_enable(s, 0); break; case VM_CMD_SEND_NMI: k->do_hw_op(s, IPMI_SEND_NMI, 0); break; case VM_CMD_FORCEOFF: qemu_system_shutdown_request(); break; } }
void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) { env->psw.addr = addr; env->psw.mask = mask; if (tcg_enabled()) { env->cc_op = (mask >> 44) & 3; } if (mask & PSW_MASK_WAIT) { S390CPU *cpu = s390_env_get_cpu(env); if (s390_cpu_halt(cpu) == 0) { #ifndef CONFIG_USER_ONLY qemu_system_shutdown_request(); #endif } } }
static BOOL WINAPI qemu_ctrl_handler(DWORD type) { #ifdef USE_ANDROID_EMU // In android, request closing the UI, instead of short-circuting down to // qemu. This will eventually call qemu_system_shutdown_request via a skin // event. skin_winsys_quit_request(); #else qemu_system_shutdown_request(); #endif // !USE_ANDROID_EMU /* Windows 7 kills application when the function returns. Sleep here to give QEMU a try for closing. Sleep period is 10000ms because Windows kills the program after 10 seconds anyway. */ Sleep(10000); return TRUE; }
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) { static const char shutdown_str[8] = "Shutdown"; static int shutdown_index = 0; switch(addr) { /* Bochs BIOS messages */ case 0x400: case 0x401: fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); exit(1); case 0x402: case 0x403: #ifdef DEBUG_BIOS fprintf(stderr, "%c", val); #endif break; case 0x8900: /* same as Bochs power off */ if (val == shutdown_str[shutdown_index]) { shutdown_index++; if (shutdown_index == 8) { shutdown_index = 0; qemu_system_shutdown_request(); } } else { shutdown_index = 0; } break; /* LGPL'ed VGA BIOS messages */ case 0x501: case 0x502: fprintf(stderr, "VGA BIOS panic, line %d\n", val); exit(1); case 0x500: case 0x503: #ifdef DEBUG_BIOS fprintf(stderr, "%c", val); #endif break; } }
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; switch(addr) { case 0x00: { int64_t d; int pmsts; pmsts = get_pmsts(s); if (pmsts & val & TMROF_EN) { /* if TMRSTS is reset, then compute the new overflow time */ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; pm_update_sci(s); } break; case 0x02: s->pmen = val; pm_update_sci(s); break; case 0x04: { int sus_typ; s->pmcntrl = val & ~(SUS_EN); if (val & SUS_EN) { /* change suspend type */ sus_typ = (val >> 10) & 3; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; default: break; } } } break; default: break; }
uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, uint64_t cpu_addr) { int cc = 0; HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n", __func__, order_code, r1, cpu_addr); /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" as parameter (input). Status (output) is always R1. */ switch (order_code) { case SIGP_SET_ARCH: /* switch arch */ break; case SIGP_SENSE: /* enumerate CPU status */ if (cpu_addr) { /* XXX implement when SMP comes */ return 3; } env->regs[r1] &= 0xffffffff00000000ULL; cc = 1; break; #if !defined(CONFIG_USER_ONLY) case SIGP_RESTART: qemu_system_reset_request(); cpu_loop_exit(env); break; case SIGP_STOP: qemu_system_shutdown_request(); cpu_loop_exit(env); break; #endif default: /* unknown sigp */ fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code); cc = 3; } return cc; }
static void hb_regs_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { uint32_t *regs = opaque; if (offset == 0xf00) { if (value == 1 || value == 2) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } else if (value == 3) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } } if (offset / 4 >= NUM_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); return; } regs[offset / 4] = value; }
static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly) { switch (op) { case IPMI_RESET_CHASSIS: if (checkonly) { return 0; } qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); return 0; case IPMI_POWEROFF_CHASSIS: if (checkonly) { return 0; } qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); return 0; case IPMI_SEND_NMI: if (checkonly) { return 0; } qmp_inject_nmi(NULL); return 0; case IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP: if (checkonly) { return 0; } qemu_system_powerdown_request(); return 0; case IPMI_POWERCYCLE_CHASSIS: case IPMI_PULSE_DIAG_IRQ: case IPMI_POWERON_CHASSIS: default: return IPMI_CC_COMMAND_NOT_SUPPORTED; } }
static void r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { r2d_fpga_t *s = opaque; switch (addr) { case PA_IRLMSK: s->irlmsk = value; update_irl(s); break; case PA_OUTPORT: s->outport = value; break; case PA_POWOFF: if (value & 1) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } break; case PA_VERREG: /* Discard writes */ break; } }
static void r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value) { r2d_fpga_t *s = opaque; switch (addr) { case PA_IRLMSK: s->irlmsk = value; update_irl(s); break; case PA_OUTPORT: s->outport = value; break; case PA_POWOFF: if (value & 1) { qemu_system_shutdown_request(); } break; case PA_VERREG: /* Discard writes */ break; } }