static DDS_ReturnCode_t sequence_get(qeocore_data_t **value, const DDS_DynamicData dyndata, qeocore_member_id_t id, DDS_DynamicType type) { DDS_ReturnCode_t ddsrc; *value = data_alloc(type, 1); if (NULL == *value) { ddsrc = DDS_RETCODE_OUT_OF_RESOURCES; } else { DDS_DynamicData seqdata; ddsrc = DDS_DynamicData_get_complex_value(dyndata, &seqdata, id); if (DDS_RETCODE_OK == ddsrc) { /* actual data was returned */ DDS_DynamicDataFactory_delete_data((*value)->d.dynamic.single_data); (*value)->d.dynamic.single_data = seqdata; } /* in case of DDS_RETCODE_NO_DATA we keep the preallocated data */ else if (DDS_RETCODE_NO_DATA != ddsrc) { qeo_log_dds_rc("DDS_DynamicData_get_complex_value", ddsrc); } } return ddsrc; }
extern unsigned long dataAvailable; /* Function prototypes */ unsigned char mp3_VS1053_attach(VOS_HANDLE spi_master_handle, unsigned char XRESET_GPIO_port, unsigned char XRESET_GPIO_pin, unsigned char DREQ_GPIO_port, unsigned char DREQ_GPIO_pin, unsigned char SDI_CS_identifier, unsigned char SCI_CS_identifier); int mp3_VS1053_detach(); int mp3_VS1053_select_control(void); int mp3_VS1053_deselect_control(void); int mp3_VS1053_select_data(void); int mp3_VS1053_deselect_data(void); int mp3_VS1053_hard_reset(void); int mp3_VS1053_soft_reset(void); int mp3_VS1053_setup(void); int mp3_VS1053_wait_for_dreq(void); int mp3_VS1053_write_reg(unsigned char reg_address, unsigned short data); int mp3_VS1053_read_reg(unsigned char reg_address, unsigned short *data); unsigned short mp3_VS1053_read_ram(unsigned short ram_address); unsigned char mp3_VS1053_write(unsigned char *buf, unsigned short num_to_write, unsigned short *num_written); unsigned char mp3_VS1053_ioctl(void *cb); void mp3_VS1053_init(unsigned char mp3VS1053DevNum, mp3_VS1053_context_t *mp3Context) { // Set up function pointers for our driver mp3_VS1053_cb.flags = 0; mp3_VS1053_cb.read = (PF_IO) NULL; mp3_VS1053_cb.write = mp3_VS1053_write; mp3_VS1053_cb.ioctl = mp3_VS1053_ioctl; mp3_VS1053_cb.interrupt = (PF_INT) NULL;
static DDS_ReturnCode_t struct_set(qeocore_data_t **data, const DDS_DynamicData dyndata, qeocore_member_id_t id) { DDS_ReturnCode_t ddsrc = DDS_RETCODE_OUT_OF_RESOURCES; if ((*data != NULL )&& ((*data)->d.dynamic.single_data != NULL)){ ddsrc = DDS_DynamicData_set_complex_value(dyndata, id, (*data)->d.dynamic.single_data); qeo_log_dds_rc("DDS_DynamicData_set_complex_value", ddsrc); } return ddsrc; }
static DDS_ReturnCode_t sequence_set(const qeocore_data_t **value, DDS_DynamicData dyndata, qeocore_member_id_t id) { DDS_ReturnCode_t ddsrc = DDS_RETCODE_ERROR; ddsrc = DDS_DynamicData_set_complex_value(dyndata, id, (*value)->d.dynamic.single_data); qeo_log_dds_rc("DDS_DynamicData_set_complex_value", ddsrc); return ddsrc; }
port vII_gpio_data_rx_pb_1 @ VII_GPIO_DATA_RX_PB_1; port vII_gpio_data_rx_pc_1 @ VII_GPIO_DATA_RX_PC_1; port vII_gpio_data_rx_pd_1 @ VII_GPIO_DATA_RX_PD_1; port vII_gpio_data_rx_pe_1 @ VII_GPIO_DATA_RX_PE_1; port vII_gpio_int_reg_en_1 @ VII_GPIO_INT_REG_EN_1; /* Global variables */ vos_driver_t mp3_VS1053_cb; mp3_VS1053_prvt_context mp3_VS1053_prvt_ctx; common_ioctl_cb_t spim_iocb;
mp3_VS1053_cb.close = (PF_CLOSE) NULL; // OK - register with device manager vos_dev_init(mp3VS1053DevNum, &mp3_VS1053_cb, NULL); // Enable GPIO control vII_gpio_sys_cntrl_1 = MASK_GPIO_EN; } unsigned char mp3_VS1053_attach(VOS_HANDLE spi_master_handle, unsigned char XRESET_GPIO_port, unsigned char XRESET_GPIO_pin, unsigned char DREQ_GPIO_port, unsigned char DREQ_GPIO_pin, unsigned char SDI_CS_identifier, unsigned char SCI_CS_identifier) { if ((XRESET_GPIO_port > PORT_E) || (DREQ_GPIO_port > PORT_E))
static DDS_ReturnCode_t struct_get(qeocore_data_t **data, const DDS_DynamicData dyndata, qeocore_member_id_t id, DDS_MemberDescriptor *mdesc) { DDS_ReturnCode_t ddsrc = DDS_RETCODE_OUT_OF_RESOURCES; *data = calloc(1, sizeof(qeocore_data_t)); if (NULL != *data) { (*data)->flags.is_single = 1; ddsrc = DDS_DynamicData_get_complex_value(dyndata, &(*data)->d.dynamic.single_data, id); if (DDS_RETCODE_NO_DATA == ddsrc) { /* no nested structure there yet, create empty one */ (*data)->d.dynamic.single_data = DDS_DynamicDataFactory_create_data(mdesc->type); qeo_log_dds_null("DDS_DynamicDataFactory_create_data", (*data)->d.dynamic.single_data); if (NULL != (*data)->d.dynamic.single_data) { ddsrc = DDS_RETCODE_OK; } } else { qeo_log_dds_rc("DDS_DynamicData_get_complex_value", ddsrc); } } if (DDS_RETCODE_OK == ddsrc) { /* take ownership of type for future use */ (*data)->d.dynamic.single_type = mdesc->type; mdesc->type = NULL; } else { if (NULL != *data) { if (NULL != (*data)->d.dynamic.single_data) { DDS_DynamicDataFactory_delete_data((*data)->d.dynamic.single_data); } free(*data); } } return ddsrc; }
#include "MP3_VS1053_defs.h" #include "devman.h" #define MP3_VS1053_BUFFER_SIZE 128 #define MASK_GPIO_EN (1 << 1) /* Port registers */ #define VII_GPIO_SYS_CNTRL_1 0x180 /* GPIO Control Register */ #define VII_GPIO_CNTRL_PORTA_1 0x181 #define VII_GPIO_CNTRL_PORTB_1 0x182 #define VII_GPIO_CNTRL_PORTC_1 0x183 #define VII_GPIO_CNTRL_PORTD_1 0x184 #define VII_GPIO_CNTRL_PORTE_1 0x185 #define VII_GPIO_DATA_TX_PA_1 0x186 #define VII_GPIO_DATA_TX_PB_1 0x187 #define VII_GPIO_DATA_TX_PC_1 0x188 #define VII_GPIO_DATA_TX_PD_1 0x189 #define VII_GPIO_DATA_TX_PE_1 0x18a #define VII_GPIO_DATA_RX_PA_1 0x18b #define VII_GPIO_DATA_RX_PB_1 0x18c #define VII_GPIO_DATA_RX_PC_1 0x18d #define VII_GPIO_DATA_RX_PD_1 0x18e #define VII_GPIO_DATA_RX_PE_1 0x18f #define VII_GPIO_INT_REG_EN_1 0x19a /* GPIO Interrupt Register */ port vII_gpio_sys_cntrl_1 @ VII_GPIO_SYS_CNTRL_1; port vII_gpio_cntrl_porta_1 @ VII_GPIO_CNTRL_PORTA_1; port vII_gpio_cntrl_portb_1 @ VII_GPIO_CNTRL_PORTB_1; port vII_gpio_cntrl_portc_1 @ VII_GPIO_CNTRL_PORTC_1; port vII_gpio_cntrl_portd_1 @ VII_GPIO_CNTRL_PORTD_1; port vII_gpio_cntrl_porte_1 @ VII_GPIO_CNTRL_PORTE_1; port vII_gpio_data_tx_pa_1 @ VII_GPIO_DATA_TX_PA_1; port vII_gpio_data_tx_pb_1 @ VII_GPIO_DATA_TX_PB_1; port vII_gpio_data_tx_pc_1 @ VII_GPIO_DATA_TX_PC_1; port vII_gpio_data_tx_pd_1 @ VII_GPIO_DATA_TX_PD_1; port vII_gpio_data_tx_pe_1 @ VII_GPIO_DATA_TX_PE_1;
static qeo_retcode_t data_member_accessor(qeocore_data_t *data, qeocore_member_id_t id, void *value, int get) { qeo_retcode_t rc = QEO_EINVAL; DDS_ReturnCode_t ddsrc; DDS_DynamicTypeMember mtype = DDS_DynamicTypeMember__alloc(); DDS_DynamicType dyntype = dtype_from_data(data, &data->d.dynamic); DDS_DynamicData dyndata = (DDS_DynamicData)sample_from_data(data); if (NULL != mtype) { ddsrc = DDS_DynamicType_get_member(dyntype, mtype, id); qeo_log_dds_rc("DDS_DynamicType_get_member", ddsrc); if (DDS_RETCODE_OK == ddsrc) { DDS_ReturnCode_t ddsrc = DDS_RETCODE_BAD_PARAMETER; DDS_MemberDescriptor mdesc = { 0 }; DDS_TypeDescriptor tdesc = { 0 }; ddsrc = DDS_DynamicTypeMember_get_descriptor(mtype, &mdesc); qeo_log_dds_rc("DDS_DynamicTypeMember_get_descriptor", ddsrc); ddsrc = DDS_DynamicType_get_descriptor(mdesc.type, &tdesc); qeo_log_dds_rc("DDS_DynamicType_get_descriptor", ddsrc); switch (tdesc.kind) { case DDS_BOOLEAN_TYPE: { if (get) { ddsrc = DDS_DynamicData_get_boolean_value(dyndata, (qeo_boolean_t *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_boolean_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_boolean_value(dyndata, id, *((qeo_boolean_t *)value)); qeo_log_dds_rc("DDS_DynamicData_set_boolean_value", ddsrc); } break; } case DDS_BYTE_TYPE: /* QEOCORE_TYPECODE_INT8 */ if (get) { ddsrc = DDS_DynamicData_get_byte_value(dyndata, (unsigned char *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_byte_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_byte_value(dyndata, id, *((unsigned char *)value)); qeo_log_dds_rc("DDS_DynamicData_set_byte_value", ddsrc); } break; case DDS_INT_16_TYPE: /* QEOCORE_TYPECODE_INT16 */ if (get) { ddsrc = DDS_DynamicData_get_int16_value(dyndata, (int16_t *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_int16_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_int16_value(dyndata, id, *((int16_t *)value)); qeo_log_dds_rc("DDS_DynamicData_set_int16_value", ddsrc); } break; case DDS_INT_32_TYPE: /* QEOCORE_TYPECODE_INT32 */ case DDS_ENUMERATION_TYPE: /* QEOCORE_TYPECODE_ENUM */ if (get) { ddsrc = DDS_DynamicData_get_int32_value(dyndata, (int32_t *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_int32_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_int32_value(dyndata, id, *((int32_t *)value)); qeo_log_dds_rc("DDS_DynamicData_set_int32_value", ddsrc); } break; case DDS_INT_64_TYPE: /* QEOCORE_TYPECODE_INT64 */ if (get) { ddsrc = DDS_DynamicData_get_int64_value(dyndata, (int64_t *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_int64_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_int64_value(dyndata, id, *((int64_t *)value)); qeo_log_dds_rc("DDS_DynamicData_set_int64_value", ddsrc); } break; case DDS_FLOAT_32_TYPE: /* QEOCORE_TYPECODE_FLOAT32 */ if (get) { ddsrc = DDS_DynamicData_get_float32_value(dyndata, (float *)value, id); qeo_log_dds_rc("DDS_DynamicData_get_float32_value", ddsrc); } else { ddsrc = DDS_DynamicData_set_float32_value(dyndata, id, *((float *)value)); qeo_log_dds_rc("DDS_DynamicData_set_float32_value", ddsrc); } break; case DDS_STRING_TYPE: /* QEOCORE_TYPECODE_STRING */ if (get) { char **string = (char **)value; int len = DDS_DynamicData_get_string_length(dyndata, id); if (len > -1) { *string = malloc(len + 1); if (NULL != *string) { ddsrc = DDS_DynamicData_get_string_value(dyndata, *string, id); qeo_log_dds_rc("DDS_DynamicData_get_string_value", ddsrc); if (DDS_RETCODE_OK != ddsrc) { free(*string); *string = NULL; } } } } else { char **string = (char **)value; ddsrc = DDS_DynamicData_set_string_value(dyndata, id, *string); qeo_log_dds_rc("DDS_DynamicData_set_string_value", ddsrc); } break; case DDS_SEQUENCE_TYPE: { /* QEOCORE_TYPECODE_SEQUENCE */ if (get) { ddsrc = sequence_get(value, dyndata, id, mdesc.type); } else { ddsrc = sequence_set(value, dyndata, id); } break; } case DDS_STRUCTURE_TYPE: { /* QEOCORE_TYPECODE_STRUCT */ qeocore_data_t **inner_data = (qeocore_data_t **)value; if (get) { ddsrc = struct_get(inner_data, dyndata, id, &mdesc); } else { ddsrc = struct_set(inner_data, dyndata, id); } break; } default: qeo_log_e("unsupported type %d", tdesc.kind); abort(); // unsupported for now break; } DDS_MemberDescriptor__clear(&mdesc); DDS_TypeDescriptor__clear(&tdesc); //TODO: Make the following code more generic and use the overall error translation function if ((DDS_RETCODE_OK == ddsrc) || (DDS_RETCODE_NO_DATA == ddsrc)){ rc = QEO_OK; } else if (DDS_RETCODE_OUT_OF_RESOURCES == ddsrc) { rc = QEO_ENOMEM; } else { rc = QEO_EFAIL; } } DDS_DynamicTypeMember__free(mtype); } return rc; }
if ((XRESET_GPIO_pin > 7) || (DREQ_GPIO_pin > 7)) return MP3_VS1053_INVALID_PARAMETER; mp3_VS1053_prvt_ctx.hSpiMaster = spi_master_handle; mp3_VS1053_prvt_ctx.XRESET_GPIO_port = XRESET_GPIO_port; mp3_VS1053_prvt_ctx.XRESET_GPIO_pin = XRESET_GPIO_pin; mp3_VS1053_prvt_ctx.DREQ_GPIO_port = DREQ_GPIO_port; mp3_VS1053_prvt_ctx.DREQ_GPIO_pin = DREQ_GPIO_pin; mp3_VS1053_prvt_ctx.SDI_CS_identifier = SDI_CS_identifier; mp3_VS1053_prvt_ctx.SCI_CS_identifier = SCI_CS_identifier; return MP3_VS1053_OK; } int mp3_VS1053_detach() { mp3_VS1053_prvt_ctx.hSpiMaster = NULL; return MP3_VS1053_OK; } int mp3_VS1053_hard_reset(void) { unsigned char mask; mask = 0x01 << mp3_VS1053_prvt_ctx.XRESET_GPIO_pin; switch (mp3_VS1053_prvt_ctx.XRESET_GPIO_port) { case PORT_A: vII_gpio_data_tx_pa_1 &= (~mask); // set the pin LOW vos_delay_msecs(3); // wait for some time vII_gpio_data_tx_pa_1 |= mask; // set the pin HIGH break; case PORT_B: vII_gpio_data_tx_pb_1 &= (~mask); // set the pin LOW vos_delay_msecs(3); // wait for some time vII_gpio_data_tx_pb_1 |= mask; // set the pin HIGH break; case PORT_C: vII_gpio_data_tx_pc_1 &= (~mask); // set the pin LOW vos_delay_msecs(3); // wait for some time vII_gpio_data_tx_pc_1 |= mask; // set the pin HIGH break; case PORT_D: vII_gpio_data_tx_pd_1 &= (~mask); // set the pin LOW vos_delay_msecs(3); // wait for some time vII_gpio_data_tx_pd_1 |= mask; // set the pin HIGH break; case PORT_E: vII_gpio_data_tx_pe_1 &= (~mask); // set the pin LOW vos_delay_msecs(3); // wait for some time vII_gpio_data_tx_pe_1 |= mask; // set the pin HIGH break; default: return MP3_VS1053_INVALID_PARAMETER; } return MP3_VS1053_OK; } int mp3_VS1053_soft_reset(void) { mp3_VS1053_write_reg(SCI_MODE, MASK_SM_RESET); // Set Reset bit in mode register vos_delay_msecs(2); // At least 2 millisecond delay mp3_VS1053_wait_for_dreq(); // wait for startup // Then set mode register and clock register again mp3_VS1053_write_reg(SCI_MODE, MASK_SM_SDINEW_VS1002); mp3_VS1053_write_reg(SCI_CLOCKF, 0x8800); vos_delay_msecs(1); // 1 millisecond delay mp3_VS1053_wait_for_dreq(); // wait for the commands to complete return MP3_VS1053_OK; } int mp3_VS1053_setup(void) { unsigned short regVal; common_ioctl_cb_t spim_iocb; // Initialize SPI pins // Reset VS1053 codec hardware mp3_VS1053_hard_reset(); // Configure VS1053 defaults mp3_VS1053_write_reg(SCI_MODE, MASK_SM_SDINEW_VS1002); mp3_VS1053_write_reg(SCI_CLOCKF, 0xe000); return 0; } // Waits for the DREQ line to go high... int mp3_VS1053_wait_for_dreq(void) { unsigned char port_value = 0, mask; int timeout = 0; mask = 0x01 << mp3_VS1053_prvt_ctx.DREQ_GPIO_pin; switch (mp3_VS1053_prvt_ctx.DREQ_GPIO_port) { case PORT_A: // Read the pin. If the pin is LOW, continue reading it until it is HIGH do { port_value = vII_gpio_data_rx_pa_1; } while ((port_value & mask) == 0); break; case PORT_B: // Read the pin. If the pin is LOW, continue reading it until it is HIGH do { port_value = vII_gpio_data_rx_pb_1; //vos_delay_msecs(1); } while ((port_value & mask) == 0); break; case PORT_C: // Read the pin. If the pin is LOW, continue reading it until it is HIGH do { port_value = vII_gpio_data_rx_pc_1; } while ((port_value & mask) == 0); break; case PORT_D: // Read the pin. If the pin is LOW, continue reading it until it is HIGH do { port_value = vII_gpio_data_rx_pd_1; } while ((port_value & mask) == 0); break; case PORT_E: // Read the pin. If the pin is LOW, continue reading it until it is HIGH do { port_value = vII_gpio_data_rx_pe_1; } while ((port_value & mask) == 0); break; default: return MP3_VS1053_INVALID_PARAMETER; } } int mp3_VS1053_select_control(void) { if (mp3_VS1053_prvt_ctx.SCI_CS_identifier == SPI_CHIP_SELECT_0) spim_iocb.ioctl_code = VOS_IOCTL_SPI_MASTER_SS_0; else if (mp3_VS1053_prvt_ctx.SCI_CS_identifier == SPI_CHIP_SELECT_1) spim_iocb.ioctl_code = VOS_IOCTL_SPI_MASTER_SS_1; spim_iocb.set.param = SPI_MASTER_SS_ENABLE; vos_dev_ioctl(mp3_VS1053_prvt_ctx.hSpiMaster, &spim_iocb); return MP3_VS1053_OK;