static inline unsigned in_reg(IVState *s, enum Reg reg) { const char *name = reg2str(reg); unsigned res; res = qpci_io_readl(s->dev, s->reg_bar, reg); g_test_message("*%s -> %x\n", name, res); return res; }
static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off) { QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev); uint32_t value; value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); if (qvirtio_is_big_endian(d)) { value = bswap32(value); } return value; }
static void ehci_port_test(struct qhc *hc, int port, uint32_t expect) { uint32_t value = qpci_io_readl(hc->dev, hc->bar, 0x64 + 4 * port); uint16_t mask = ~(PORTSC_CSC | PORTSC_PEDC | PORTSC_OCC); #if 0 fprintf(stderr, "%s: %d, have 0x%08x, want 0x%08x\n", __func__, port, value & mask, expect & mask); #endif g_assert((value & mask) == (expect & mask)); }
static uint32_t qvirtio_pci_get_features(QVirtioDevice *d) { QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev); return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES); }
static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t addr) { QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d; return qpci_io_readl(dev->pdev, (void *)(uintptr_t)addr); }
static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d) { QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d; return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_PCI_GUEST_FEATURES); }