/* * TODO: * * This whole routine should be removed until we fully convert the ICH SPI * driver to DM and make use of DT to pass the bios control register offset */ static void unprotect_spi_flash(void) { u32 bc; qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); bc |= 0x1; /* unprotect the flash */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); }
static void quark_setup_bars(void) { /* GPIO - D31:F0:R44h */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, CONFIG_GPIO_BASE | IO_BAR_EN); /* ACPI PM1 Block - D31:F0:R48h */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, CONFIG_ACPI_PM1_BASE | IO_BAR_EN); /* GPE0 - D31:F0:R4Ch */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); /* WDT - D31:F0:R84h */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, CONFIG_WDT_BASE | IO_BAR_EN); /* RCBA - D31:F0:RF0h */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, CONFIG_RCBA_BASE | MEM_BAR_EN); /* ACPI P Block - Msg Port 04:R70h */ msg_port_write(MSG_PORT_RMU, PBLK_BA, CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); /* SPI DMA - Msg Port 04:R7Ah */ msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, CONFIG_SPI_DMA_BASE | IO_BAR_EN); /* PCIe ECAM */ msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); }
static void quark_pcie_init(void) { u32 val; /* PCIe upstream non-posted & posted request size */ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, CCFG_UPRS | CCFG_UNRS); qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, CCFG_UPRS | CCFG_UNRS); /* PCIe packet fast transmit mode (IPF) */ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); /* PCIe message bus idle counter (SBIC) */ qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); val |= MBC_SBIC; qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); val |= MBC_SBIC; qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); }