static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg)
{
const struct qtnf_pcie_pearl_state *ps = arg;
const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
void __iomem *reg = ps->base.sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
qtnf_non_posted_write(data, reg);
}
static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps)
{
void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
u32 cfg;
cfg = readl(reg);
cfg &= ~PEARL_ASSERT_INTX;
qtnf_non_posted_write(cfg, reg);
}
static void qtnf_ipc_gen_ep_int(void *arg)
{
const struct qtnf_pcie_bus_priv *priv = arg;
const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
void __iomem *reg = priv->sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
qtnf_non_posted_write(data, reg);
}
static void qtnf_deassert_intx(struct qtnf_pcie_bus_priv *priv)
{
void __iomem *reg = priv->sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
u32 cfg;
cfg = readl(reg);
cfg &= ~PEARL_ASSERT_INTX;
qtnf_non_posted_write(cfg, reg);
}
static void qtnf_pearl_reset_ep(struct qtnf_pcie_pearl_state *ps)
{
const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
void __iomem *reg = ps->base.sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
qtnf_non_posted_write(data, reg);
msleep(QTN_EP_RESET_WAIT_MS);
pci_restore_state(ps->base.pdev);
}
static void qtnf_reset_card(struct qtnf_pcie_bus_priv *priv)
{
const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
void __iomem *reg = priv->sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
qtnf_non_posted_write(data, reg);
msleep(QTN_EP_RESET_WAIT_MS);
pci_restore_state(priv->pdev);
}
static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data)
{
struct qtnf_bus *bus = (struct qtnf_bus *)data;
struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
struct qtnf_pcie_bus_priv *priv = &ps->base;
u32 status;
priv->pcie_irq_count++;
status = readl(PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_in);
qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_out);
if (!(status & ps->pcie_irq_mask))
goto irq_done;
if (status & PCIE_HDP_INT_RX_BITS)
ps->pcie_irq_rx_count++;
if (status & PCIE_HDP_INT_TX_BITS)
ps->pcie_irq_tx_count++;
if (status & PCIE_HDP_INT_HHBM_UF)
ps->pcie_irq_uf_count++;
if (status & PCIE_HDP_INT_RX_BITS) {
qtnf_dis_rxdone_irq(ps);
napi_schedule(&bus->mux_napi);
}
if (status & PCIE_HDP_INT_TX_BITS) {
qtnf_dis_txdone_irq(ps);
tasklet_hi_schedule(&priv->reclaim_tq);
}
irq_done:
/* H/W workaround: clean all bits, not only enabled */
qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
if (!priv->msi_enabled)
qtnf_deassert_intx(ps);
return IRQ_HANDLED;
}
static void qtnf_clear_state(__le32 __iomem *reg, u32 state)
{
u32 s = readl(reg);
qtnf_non_posted_write(s & ~state, reg);
}
static void qtnf_set_state(__le32 __iomem *reg, u32 state)
{
u32 s = readl(reg);
qtnf_non_posted_write(state | s, reg);
}
