void* r300_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer *transfer)
{
struct r300_context *r300 = r300_context(ctx);
struct radeon_winsys *rws = (struct radeon_winsys *)ctx->winsys;
struct r300_transfer *r300transfer = r300_transfer(transfer);
struct r300_resource *tex = r300_resource(transfer->resource);
char *map;
enum pipe_format format = tex->b.b.b.format;
if (r300transfer->linear_texture) {
/* The detiled texture is of the same size as the region being mapped
* (no offset needed). */
return rws->buffer_map(r300transfer->linear_texture->buf,
r300->cs,
transfer->usage);
} else {
/* Tiling is disabled. */
map = rws->buffer_map(tex->buf, r300->cs,
transfer->usage);
if (!map) {
return NULL;
}
return map + r300_transfer(transfer)->offset +
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
}
static void r300_draw_vbo(struct pipe_context* pipe,
const struct pipe_draw_info *info)
{
struct r300_context* r300 = r300_context(pipe);
if (!r300->velems->count || !r300->vertex_buffer_count)
return;
if (info->indexed && r300->index_buffer.buffer) {
unsigned offset;
assert(r300->index_buffer.offset % r300->index_buffer.index_size == 0);
offset = r300->index_buffer.offset / r300->index_buffer.index_size;
r300_draw_range_elements(pipe,
r300->index_buffer.buffer,
r300->index_buffer.index_size,
info->index_bias,
info->min_index,
info->max_index,
info->mode,
info->start + offset,
info->count);
}
else {
r300_draw_arrays(pipe,
info->mode,
info->start,
info->count);
}
}
/* Clear a region of a depth stencil surface. */
static void r300_clear_depth_stencil(struct pipe_context *pipe,
struct pipe_surface *dst,
unsigned clear_flags,
double depth,
unsigned stencil,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
if (r300->zmask_in_use && !r300->locked_zbuffer) {
if (fb->zsbuf->texture == dst->texture) {
r300_decompress_zmask(r300);
}
}
/* XXX Do not decompress ZMask of the currently-set zbuffer. */
r300_blitter_begin(r300, R300_CLEAR_SURFACE |
(render_condition_enabled ? 0 : R300_IGNORE_RENDER_COND));
util_blitter_clear_depth_stencil(r300->blitter, dst, clear_flags, depth, stencil,
dstx, dsty, width, height);
r300_blitter_end(r300);
}
/* Flush a depth stencil buffer. */
void r300_flush_depth_stencil(struct pipe_context *pipe,
struct pipe_resource *dst,
unsigned level,
unsigned layer)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_surface *dstsurf, surf_tmpl;
struct r300_texture *tex = r300_texture(dst);
if (!tex->zmask_mem[level])
return;
if (!tex->zmask_in_use[level])
return;
surf_tmpl.format = dst->format;
surf_tmpl.usage = PIPE_BIND_DEPTH_STENCIL;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
dstsurf = pipe->create_surface(pipe, dst, &surf_tmpl);
r300->z_decomp_rd = TRUE;
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_flush_depth_stencil(r300->blitter, dstsurf);
r300_blitter_end(r300);
r300->z_decomp_rd = FALSE;
tex->zmask_in_use[level] = FALSE;
}
static void *
r300_buffer_transfer_map( struct pipe_context *pipe,
struct pipe_transfer *transfer )
{
struct r300_context *r300 = r300_context(pipe);
struct r300_screen *r300screen = r300_screen(pipe->screen);
struct radeon_winsys *rws = r300screen->rws;
struct r300_resource *rbuf = r300_resource(transfer->resource);
uint8_t *map;
enum pipe_transfer_usage usage;
if (rbuf->b.b.user_ptr)
return rbuf->b.b.user_ptr + transfer->box.x;
if (rbuf->constant_buffer)
return (uint8_t *) rbuf->constant_buffer + transfer->box.x;
/* Buffers are never used for write, therefore mapping for read can be
* unsynchronized. */
usage = transfer->usage;
if (!(usage & PIPE_TRANSFER_WRITE)) {
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
}
map = rws->buffer_map(rbuf->cs_buf, r300->cs, usage);
if (map == NULL)
return NULL;
return map + transfer->box.x;
}
static void r300_buffer_transfer_unmap( struct pipe_context *pipe,
struct pipe_transfer *transfer )
{
struct r300_context *r300 = r300_context(pipe);
util_slab_free(&r300->pool_transfers, transfer);
}
static void r300_set_sampler_textures(struct pipe_context* pipe,
unsigned count,
struct pipe_texture** texture)
{
struct r300_context* r300 = r300_context(pipe);
int i;
/* XXX magic num */
if (count > 8) {
return;
}
r300->context.flush(&r300->context, 0, NULL);
for (i = 0; i < count; i++) {
if (r300->textures[i] != (struct r300_texture*)texture[i]) {
pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
texture[i]);
r300->dirty_state |= (R300_NEW_TEXTURE << i);
}
}
for (i = count; i < 8; i++) {
if (r300->textures[i]) {
pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
NULL);
r300->dirty_state |= (R300_NEW_TEXTURE << i);
}
}
r300->texture_count = count;
}
static void r300_set_viewport_state(struct pipe_context* pipe,
const struct pipe_viewport_state* state)
{
struct r300_context* r300 = r300_context(pipe);
/* Do the transform in HW. */
r300->viewport_state->vte_control = R300_VTX_W0_FMT;
if (state->scale[0] != 1.0f) {
r300->viewport_state->xscale = state->scale[0];
r300->viewport_state->vte_control |= R300_VPORT_X_SCALE_ENA;
}
if (state->scale[1] != 1.0f) {
r300->viewport_state->yscale = state->scale[1];
r300->viewport_state->vte_control |= R300_VPORT_Y_SCALE_ENA;
}
if (state->scale[2] != 1.0f) {
r300->viewport_state->zscale = state->scale[2];
r300->viewport_state->vte_control |= R300_VPORT_Z_SCALE_ENA;
}
if (state->translate[0] != 0.0f) {
r300->viewport_state->xoffset = state->translate[0];
r300->viewport_state->vte_control |= R300_VPORT_X_OFFSET_ENA;
}
if (state->translate[1] != 0.0f) {
r300->viewport_state->yoffset = state->translate[1];
r300->viewport_state->vte_control |= R300_VPORT_Y_OFFSET_ENA;
}
if (state->translate[2] != 0.0f) {
r300->viewport_state->zoffset = state->translate[2];
r300->viewport_state->vte_control |= R300_VPORT_Z_OFFSET_ENA;
}
r300->dirty_state |= R300_NEW_VIEWPORT;
}
static void*
r300_create_sampler_state(struct pipe_context* pipe,
const struct pipe_sampler_state* state)
{
struct r300_context* r300 = r300_context(pipe);
struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
int lod_bias;
sampler->filter0 |=
(r300_translate_wrap(state->wrap_s) << R300_TX_WRAP_S_SHIFT) |
(r300_translate_wrap(state->wrap_t) << R300_TX_WRAP_T_SHIFT) |
(r300_translate_wrap(state->wrap_r) << R300_TX_WRAP_R_SHIFT);
sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
state->mag_img_filter,
state->min_mip_filter);
lod_bias = CLAMP((int)(state->lod_bias * 32), -(1 << 9), (1 << 9) - 1);
sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT;
sampler->filter1 |= r300_anisotropy(state->max_anisotropy);
util_pack_color(state->border_color, PIPE_FORMAT_A8R8G8B8_UNORM,
&sampler->border_color);
/* R500-specific fixups and optimizations */
if (r300_screen(r300->context.screen)->caps->is_r500) {
sampler->filter1 |= R500_BORDER_FIX;
}
return (void*)sampler;
}
static void r300_blit(struct pipe_context *pipe,
const struct pipe_blit_info *blit_info)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct pipe_blit_info info = *blit_info;
/* Decompress ZMASK. */
if (r300->zmask_in_use && !r300->locked_zbuffer) {
if (fb->zsbuf->texture == info.src.resource ||
fb->zsbuf->texture == info.dst.resource) {
r300_decompress_zmask(r300);
}
}
/* Blit a combined depth-stencil resource as color.
* S8Z24 is the only supported stencil format. */
if ((info.mask & PIPE_MASK_S) &&
info.src.format == PIPE_FORMAT_S8_UINT_Z24_UNORM &&
info.dst.format == PIPE_FORMAT_S8_UINT_Z24_UNORM) {
info.src.format = PIPE_FORMAT_B8G8R8A8_UNORM;
info.dst.format = PIPE_FORMAT_B8G8R8A8_UNORM;
if (info.mask & PIPE_MASK_Z) {
info.mask = PIPE_MASK_RGBA; /* depth+stencil */
} else {
info.mask = PIPE_MASK_B; /* stencil only */
}
}
r300_blitter_begin(r300, R300_BLIT);
util_blitter_blit(r300->blitter, &info);
r300_blitter_end(r300);
}
boolean r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
unsigned start, unsigned count)
{
struct r300_context* r300 = r300_context(pipe);
if (!u_trim_pipe_prim(mode, &count)) {
return FALSE;
}
if (count > 65535) {
return FALSE;
}
r300_update_derived_state(r300);
if (!r300_setup_vertex_buffers(r300)) {
return FALSE;
}
setup_vertex_attributes(r300);
r300_emit_dirty_state(r300);
r300_emit_aos(r300, start);
r300_emit_draw_arrays(r300, mode, count);
return TRUE;
}
/* SW TCL arrays, using Draw. */
boolean r300_swtcl_draw_arrays(struct pipe_context* pipe,
unsigned mode,
unsigned start,
unsigned count)
{
struct r300_context* r300 = r300_context(pipe);
int i;
if (!u_trim_pipe_prim(mode, &count)) {
return FALSE;
}
for (i = 0; i < r300->vertex_buffer_count; i++) {
void* buf = pipe_buffer_map(pipe->screen,
r300->vertex_buffer[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_vertex_buffer(r300->draw, i, buf);
}
draw_set_mapped_element_buffer(r300->draw, 0, NULL);
draw_set_mapped_constant_buffer(r300->draw,
r300->shader_constants[PIPE_SHADER_VERTEX].constants,
r300->shader_constants[PIPE_SHADER_VERTEX].count *
(sizeof(float) * 4));
draw_arrays(r300->draw, mode, start, count);
for (i = 0; i < r300->vertex_buffer_count; i++) {
pipe_buffer_unmap(pipe->screen, r300->vertex_buffer[i].buffer);
draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
}
return TRUE;
}
/* Bind DSA state. */
static void r300_bind_dsa_state(struct pipe_context* pipe,
void* state)
{
struct r300_context* r300 = r300_context(pipe);
r300->dsa_state = (struct r300_dsa_state*)state;
r300->dirty_state |= R300_NEW_DSA;
}
/* Bind blend state. */
static void r300_bind_blend_state(struct pipe_context* pipe,
void* state)
{
struct r300_context* r300 = r300_context(pipe);
r300->blend_state = (struct r300_blend_state*)state;
r300->dirty_state |= R300_NEW_BLEND;
}
/* SW TCL elements, using Draw. */
static void r300_swtcl_draw_vbo(struct pipe_context* pipe,
const struct pipe_draw_info *info)
{
struct r300_context* r300 = r300_context(pipe);
struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
struct pipe_transfer *ib_transfer = NULL;
int i;
void *indices = NULL;
boolean indexed = info->indexed && r300->vbuf_mgr->index_buffer.buffer;
if (r300->skip_rendering) {
return;
}
r300_update_derived_state(r300);
r300_reserve_cs_dwords(r300,
PREP_EMIT_STATES | PREP_EMIT_VARRAYS_SWTCL |
(indexed ? PREP_INDEXED : 0),
indexed ? 256 : 6);
for (i = 0; i < r300->vbuf_mgr->nr_vertex_buffers; i++) {
if (r300->vbuf_mgr->vertex_buffer[i].buffer) {
void *buf = pipe_buffer_map(pipe,
r300->vbuf_mgr->vertex_buffer[i].buffer,
PIPE_TRANSFER_READ |
PIPE_TRANSFER_UNSYNCHRONIZED,
&vb_transfer[i]);
draw_set_mapped_vertex_buffer(r300->draw, i, buf);
}
}
if (indexed) {
indices = pipe_buffer_map(pipe, r300->vbuf_mgr->index_buffer.buffer,
PIPE_TRANSFER_READ |
PIPE_TRANSFER_UNSYNCHRONIZED, &ib_transfer);
}
draw_set_mapped_index_buffer(r300->draw, indices);
r300->draw_vbo_locked = TRUE;
r300->draw_first_emitted = FALSE;
draw_vbo(r300->draw, info);
draw_flush(r300->draw);
r300->draw_vbo_locked = FALSE;
for (i = 0; i < r300->vbuf_mgr->nr_vertex_buffers; i++) {
if (r300->vbuf_mgr->vertex_buffer[i].buffer) {
pipe_buffer_unmap(pipe, vb_transfer[i]);
draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
}
}
if (indexed) {
pipe_buffer_unmap(pipe, ib_transfer);
draw_set_mapped_index_buffer(r300->draw, NULL);
}
}
static void r300_blit(struct pipe_context *pipe,
const struct pipe_blit_info *blit)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct pipe_blit_info info = *blit;
/* MSAA resolve. */
if (info.src.resource->nr_samples > 1 &&
!util_format_is_depth_or_stencil(info.src.resource->format)) {
r300_msaa_resolve(pipe, &info);
return;
}
/* Can't read MSAA textures. */
if (info.src.resource->nr_samples > 1) {
return;
}
/* Blit a combined depth-stencil resource as color.
* S8Z24 is the only supported stencil format. */
if ((info.mask & PIPE_MASK_S) &&
info.src.format == PIPE_FORMAT_S8_UINT_Z24_UNORM &&
info.dst.format == PIPE_FORMAT_S8_UINT_Z24_UNORM) {
if (info.dst.resource->nr_samples > 1) {
/* Cannot do that with MSAA buffers. */
info.mask &= ~PIPE_MASK_S;
if (!(info.mask & PIPE_MASK_Z)) {
return;
}
} else {
/* Single-sample buffer. */
info.src.format = PIPE_FORMAT_B8G8R8A8_UNORM;
info.dst.format = PIPE_FORMAT_B8G8R8A8_UNORM;
if (info.mask & PIPE_MASK_Z) {
info.mask = PIPE_MASK_RGBA; /* depth+stencil */
} else {
info.mask = PIPE_MASK_B; /* stencil only */
}
}
}
/* Decompress ZMASK. */
if (r300->zmask_in_use && !r300->locked_zbuffer) {
if (fb->zsbuf->texture == info.src.resource ||
fb->zsbuf->texture == info.dst.resource) {
r300_decompress_zmask(r300);
}
}
r300_blitter_begin(r300, R300_BLIT |
(info.render_condition_enable ? 0 : R300_IGNORE_RENDER_COND));
util_blitter_blit(r300->blitter, &info);
r300_blitter_end(r300);
}
static void r300_destroy_context(struct pipe_context* context)
{
struct r300_context* r300 = r300_context(context);
if (r300->cs && r300->hyperz_enabled) {
r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, FALSE);
}
if (r300->cs && r300->cmask_access) {
r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_CMASK_ACCESS, FALSE);
}
if (r300->blitter)
util_blitter_destroy(r300->blitter);
if (r300->draw)
draw_destroy(r300->draw);
if (r300->uploader)
u_upload_destroy(r300->uploader);
/* XXX: This function assumes r300->query_list was initialized */
r300_release_referenced_objects(r300);
if (r300->cs)
r300->rws->cs_destroy(r300->cs);
if (r300->ctx)
r300->rws->ctx_destroy(r300->ctx);
rc_destroy_regalloc_state(&r300->fs_regalloc_state);
/* XXX: No way to tell if this was initialized or not? */
util_slab_destroy(&r300->pool_transfers);
/* Free the structs allocated in r300_setup_atoms() */
if (r300->aa_state.state) {
FREE(r300->aa_state.state);
FREE(r300->blend_color_state.state);
FREE(r300->clip_state.state);
FREE(r300->fb_state.state);
FREE(r300->gpu_flush.state);
FREE(r300->hyperz_state.state);
FREE(r300->invariant_state.state);
FREE(r300->rs_block_state.state);
FREE(r300->sample_mask.state);
FREE(r300->scissor_state.state);
FREE(r300->textures_state.state);
FREE(r300->vap_invariant_state.state);
FREE(r300->viewport_state.state);
FREE(r300->ztop_state.state);
FREE(r300->fs_constants.state);
FREE(r300->vs_constants.state);
if (!r300->screen->caps.has_tcl) {
FREE(r300->vertex_stream_state.state);
}
}
FREE(r300);
}
void r300_flush(struct pipe_context *pipe,
unsigned flags,
struct pipe_fence_handle **fence)
{
struct r300_context *r300 = r300_context(pipe);
if (r300->screen->info.drm_minor >= 12) {
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
}
if (r300->dirty_hw) {
r300_flush_and_cleanup(r300, flags, fence);
} else {
if (fence) {
/* We have to create a fence object, but the command stream is empty
* and we cannot emit an empty CS. Let's write to some reg. */
CS_LOCALS(r300);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
r300->rws->cs_flush(r300->cs, flags, fence, 0);
} else {
/* Even if hw is not dirty, we should at least reset the CS in case
* the space checking failed for the first draw operation. */
r300->rws->cs_flush(r300->cs, flags, NULL, 0);
}
}
/* Update Hyper-Z status. */
if (r300->hyperz_enabled) {
/* If there was a Z clear, keep Hyper-Z access. */
if (r300->num_z_clears) {
r300->hyperz_time_of_last_flush = os_time_get();
r300->num_z_clears = 0;
} else if (r300->hyperz_time_of_last_flush - os_time_get() > 2000000) {
/* If there hasn't been a Z clear for 2 seconds, revoke Hyper-Z access. */
r300->hiz_in_use = FALSE;
/* Decompress the Z buffer. */
if (r300->zmask_in_use) {
if (r300->locked_zbuffer) {
r300_decompress_zmask_locked(r300);
} else {
r300_decompress_zmask(r300);
}
if (fence && *fence)
r300->rws->fence_reference(fence, NULL);
r300_flush_and_cleanup(r300, flags, fence);
}
/* Revoke Hyper-Z access, so that some other process can take it. */
r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS,
FALSE);
r300->hyperz_enabled = FALSE;
}
}
}
static void r300_draw_vbo(struct pipe_context* pipe,
const struct pipe_draw_info *dinfo)
{
struct r300_context* r300 = r300_context(pipe);
struct pipe_draw_info info = *dinfo;
info.indexed = info.indexed;
if (r300->skip_rendering ||
!u_trim_pipe_prim(info.mode, &info.count)) {
return;
}
r300_update_derived_state(r300);
/* Draw. */
if (info.indexed) {
unsigned max_count = r300_max_vertex_count(r300);
if (!max_count) {
fprintf(stderr, "r300: Skipping a draw command. There is a buffer "
" which is too small to be used for rendering.\n");
return;
}
if (max_count == ~0) {
/* There are no per-vertex vertex elements. Use the hardware maximum. */
max_count = 0xffffff;
}
info.max_index = max_count - 1;
info.start += r300->index_buffer.offset / r300->index_buffer.index_size;
if (info.instance_count <= 1) {
if (info.count <= 8 &&
r300->index_buffer.user_buffer) {
r300_draw_elements_immediate(r300, &info);
} else {
r300_draw_elements(r300, &info, -1);
}
} else {
r300_draw_elements_instanced(r300, &info);
}
} else {
if (info.instance_count <= 1) {
if (immd_is_good_idea(r300, info.count)) {
r300_draw_arrays_immediate(r300, &info);
} else {
r300_draw_arrays(r300, &info, -1);
}
} else {
r300_draw_arrays_instanced(r300, &info);
}
}
}
static void r300_end_query(struct pipe_context* pipe,
struct pipe_query* query)
{
struct r300_context* r300 = r300_context(pipe);
struct r300_query* q = (struct r300_query*)query;
CS_LOCALS(r300);
BEGIN_CS(4);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_RELOC(q->buf, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_CS;
}
/* Clear a region of a color surface to a constant value. */
static void r300_clear_render_target(struct pipe_context *pipe,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height)
{
struct r300_context *r300 = r300_context(pipe);
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_clear_render_target(r300->blitter, dst, color,
dstx, dsty, width, height);
r300_blitter_end(r300);
}
static unsigned r300_texture_is_referenced(struct pipe_context *context,
struct pipe_resource *texture,
unsigned face, unsigned level)
{
struct r300_context *r300 = r300_context(context);
struct r300_texture *rtex = (struct r300_texture *)texture;
if (r300->rws->cs_is_buffer_referenced(r300->cs,
rtex->buffer, R300_REF_CS))
return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
return PIPE_UNREFERENCED;
}
void r300_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer *transfer)
{
struct radeon_winsys *rws = r300_context(ctx)->rws;
struct r300_transfer *r300transfer = r300_transfer(transfer);
struct r300_resource *tex = r300_resource(transfer->resource);
if (r300transfer->linear_texture) {
rws->buffer_unmap(r300transfer->linear_texture->cs_buf);
} else {
rws->buffer_unmap(tex->cs_buf);
}
}
static void r300_set_clip_state(struct pipe_context* pipe,
const struct pipe_clip_state* state)
{
struct r300_context* r300 = r300_context(pipe);
if (r300_screen(pipe->screen)->caps->has_tcl) {
r300->clip_state = *state;
r300->dirty_state |= R300_NEW_CLIP;
} else {
draw_flush(r300->draw);
draw_set_clip_state(r300->draw, state);
}
}
static void
r300_set_framebuffer_state(struct pipe_context* pipe,
const struct pipe_framebuffer_state* state)
{
struct r300_context* r300 = r300_context(pipe);
if (r300->draw) {
draw_flush(r300->draw);
}
r300->framebuffer_state = *state;
r300->dirty_state |= R300_NEW_FRAMEBUFFERS;
}
/* SW TCL elements, using Draw. */
static void r300_swtcl_draw_vbo(struct pipe_context* pipe,
const struct pipe_draw_info *info)
{
struct r300_context* r300 = r300_context(pipe);
if (r300->skip_rendering) {
return;
}
r300_update_derived_state(r300);
draw_vbo(r300->draw, info);
draw_flush(r300->draw);
}
/* Copy a block of pixels from one surface to another using HW. */
static void r300_hw_copy_region(struct pipe_context* pipe,
struct pipe_resource *dst,
unsigned dst_level,
unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box)
{
struct r300_context* r300 = r300_context(pipe);
r300_blitter_begin(r300, R300_COPY);
util_blitter_copy_texture(r300->blitter, dst, dst_level, dstx, dsty, dstz,
src, src_level, src_box, TRUE);
r300_blitter_end(r300);
}
static void r300_set_vertex_buffers(struct pipe_context* pipe,
unsigned count,
const struct pipe_vertex_buffer* buffers)
{
struct r300_context* r300 = r300_context(pipe);
memcpy(r300->vertex_buffer, buffers,
sizeof(struct pipe_vertex_buffer) * count);
r300->vertex_buffer_count = count;
if (r300->draw) {
draw_flush(r300->draw);
draw_set_vertex_buffers(r300->draw, count, buffers);
}
}
/* Clear a region of a color surface to a constant value. */
static void r300_clear_render_target(struct pipe_context *pipe,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
struct r300_context *r300 = r300_context(pipe);
r300_blitter_begin(r300, R300_CLEAR_SURFACE |
(render_condition_enabled ? 0 : R300_IGNORE_RENDER_COND));
util_blitter_clear_render_target(r300->blitter, dst, color,
dstx, dsty, width, height);
r300_blitter_end(r300);
}
/* Clear a region of a depth stencil surface. */
static void r300_clear_depth_stencil(struct pipe_context *pipe,
struct pipe_surface *dst,
unsigned clear_flags,
double depth,
unsigned stencil,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height)
{
struct r300_context *r300 = r300_context(pipe);
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_clear_depth_stencil(r300->blitter, dst, clear_flags, depth, stencil,
dstx, dsty, width, height);
r300_blitter_end(r300);
}