// ================================================ ====== ==== ==== == =
//! Apply the preconditioner to an Epetra_MultiVector X, puts the result in Y
int ML_Epetra::FaceMatrixFreePreconditioner::ApplyInverse(const Epetra_MultiVector& B_, Epetra_MultiVector& X) const{
const Epetra_MultiVector *B;
Epetra_MultiVector *Bcopy=0;
/* Sanity Checks */
int NumVectors=B_.NumVectors();
if (!B_.Map().SameAs(*FaceDomainMap_)) ML_CHK_ERR(-1);
if (NumVectors != X.NumVectors()) ML_CHK_ERR(-1);
Epetra_MultiVector r_edge(*FaceDomainMap_,NumVectors,false);
Epetra_MultiVector e_edge(*FaceDomainMap_,NumVectors,false);
Epetra_MultiVector e_node(*CoarseMap_,NumVectors,false);
Epetra_MultiVector r_node(*CoarseMap_,NumVectors,false);
/* Deal with the B==X case */
if (B_.Pointers()[0] == X.Pointers()[0]){
Bcopy=new Epetra_MultiVector(B_);
B=Bcopy;
X.PutScalar(0.0);
}
else B=&B_;
for(int i=0;i<num_cycles;i++){
/* Pre-smoothing */
#ifdef HAVE_ML_IFPACK
if(Smoother_) ML_CHK_ERR(Smoother_->ApplyInverse(*B,X));
#endif
if(MaxLevels > 0){
if(i != 0
#ifdef HAVE_ML_IFPACK
|| Smoother_
#endif
){
/* Calculate Residual (r_e = b - (S+M+Addon) * x) */
ML_CHK_ERR(Operator_->Apply(X,r_edge));
ML_CHK_ERR(r_edge.Update(1.0,*B,-1.0));
/* Xfer to coarse grid (r_n = P' * r_e) */
ML_CHK_ERR(Prolongator_->Multiply(true,r_edge,r_node));
}
else{
/* Xfer to coarse grid (r_n = P' * r_e) */
ML_CHK_ERR(Prolongator_->Multiply(true,*B,r_node));
}
/* AMG on coarse grid (e_n = (CoarseMatrix)^{-1} r_n) */
ML_CHK_ERR(CoarsePC->ApplyInverse(r_node,e_node));
/* Xfer back to fine grid (e_e = P * e_n) */
ML_CHK_ERR(Prolongator_->Multiply(false,e_node,e_edge));
/* Add in correction (x = x + e_e) */
ML_CHK_ERR(X.Update(1.0,e_edge,1.0));
}/*end if*/
/* Post-Smoothing */
#ifdef HAVE_ML_IFPACK
if(Smoother_) ML_CHK_ERR(Smoother_->ApplyInverse(*B,X));
#endif
}/*end for*/
/* Cleanup */
if(Bcopy) delete Bcopy;
return 0;
}/*end ApplyInverse*/
* Print the DRAM routing info for one base/limit pair.
*
* Show base, limit, dest node, dest link on that node, read and write
* enable, and interleave information.
*
* @param level Printing level
* @param which Register number
* @param base Base register
* @param lim Limit register
*/
static void showdram(int level, u8 which, u32 base, u32 lim)
{
printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
which, (((u64) base & 0xffff0000) << 8),
(((u64) lim & 0xffff0000) << 8) + 0xffffff,
r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
}
/**
* Print the config routing info for a config register.
*
* Show base, limit, dest node, dest link on that node, read and write
* enable, and device number compare enable
*
* @param level Printing level
* @param which Register number
* @param reg Config register
*/
static void showconfig(int level, u8 which, u32 reg)
{
/* Don't use r_node() and r_link() here. */
