C++ (Cpp) rcc_set_ppre Examples

Example #1

File: main.c Project: area3001/knixx

static void clk_tree_setup(void)
{
	/* cf. rcc_clock_setup_in_hsi_out_48mhz */
	rcc_osc_on(RCC_HSI);
	rcc_wait_for_osc_ready(RCC_HSI);
	rcc_set_sysclk_source(RCC_HSI);
	rcc_osc_on(RCC_HSE);
	rcc_wait_for_osc_ready(RCC_HSE);
	rcc_osc_off(RCC_PLL);
	rcc_wait_for_osc_not_ready(RCC_PLL);
	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
#ifdef NUCLEO
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);
#else
	/* 16MHz * 3 = 48MHz */
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL3);
#endif
	rcc_set_pll_source(RCC_HSE);
	rcc_osc_on(RCC_PLL);
	rcc_wait_for_osc_ready(RCC_PLL);
	rcc_set_sysclk_source(RCC_PLL);
	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
	rcc_apb1_frequency = 48000000UL;
	rcc_ahb_frequency = 48000000UL;
	rcc_set_usbclk_source(RCC_PLL);
}

Example #2

File: clocksource.c Project: spcfa/OpenGround_a7105

void clocksource_hse_in_8_out_48(void) {
    // see
    // https://www.mikrocontroller.net/attachment/322047/Clock_Control.png
    // or RM00091 p. 98

    // enable internal high-speed oscillator
    rcc_osc_on(RCC_HSI);
    rcc_wait_for_osc_ready(RCC_HSI);

    // Select HSI as SYSCLK source.
    rcc_set_sysclk_source(RCC_CFGR_SW_HSI);

    // Enable external high-speed oscillator 8MHz
    rcc_osc_on(RCC_HSE);
    rcc_wait_for_osc_ready(RCC_HSE);
    rcc_set_sysclk_source(RCC_CFGR_SW_HSE);

    // set prescalers for AHB, ADC, ABP1, ABP2.
    // Do this before touching the PLL
    rcc_set_hpre(RCC_CFGR_HPRE_NODIV);      // 48Mhz (max 72)
    rcc_set_ppre(RCC_CFGR_PPRE_DIV2);       // 24Mhz (max 36)

    // sysclk runs with 48MHz -> 1 waitstates.
    // * 0WS from 0-24MHz
    // * 1WS from 24-48MHz
    // * 2WS from 48-72MHz
    flash_set_ws(FLASH_ACR_LATENCY_1WS);

    // set the PLL multiplication factor to 6
    // pll source is hse
    RCC_CFGR |= RCC_CFGR_PLLSRC;
    // pll prediv = 1
    rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV);
    // 8MHz (external) * 6 (multiplier) = 48MHz
    rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);

    // enable PLL oscillator and wait for it to stabilize.
    rcc_osc_on(RCC_PLL);
    rcc_wait_for_osc_ready(RCC_PLL);

    // select PLL as SYSCLK source.
    rcc_set_sysclk_source(RCC_PLL);

    // set the peripheral clock frequencies used */
    rcc_ahb_frequency  = 48000000;
    rcc_apb1_frequency = 24000000;

    // When PPRE is set to something != NODIV
    // TIM input clock is apb clkspeed*2 (see RM00091 p98)
    rcc_timer_frequency = 2*rcc_apb1_frequency;
}

Example #3

File: rcc.c Project: LaurentBa/libopencm3-freertos

void rcc_clock_setup_in_hsi_out_8mhz(void)
{
	rcc_osc_on(HSI);
	rcc_wait_for_osc_ready(HSI);
	rcc_set_sysclk_source(HSI);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);

	rcc_ppre_frequency = 8000000;
	rcc_core_frequency = 8000000;
}

Example #4

File: rcc.c Project: ChenXuJasper/libopencm3

void rcc_clock_setup_in_hsi48_out_48mhz(void)
{
	rcc_osc_on(RCC_HSI48);
	rcc_wait_for_osc_ready(RCC_HSI48);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);

	rcc_set_sysclk_source(RCC_HSI48);

	rcc_apb1_frequency = 48000000;
	rcc_ahb_frequency = 48000000;
}

Example #5

File: rcc.c Project: LaurentBa/libopencm3-freertos

void rcc_clock_setup_in_hsi_out_48mhz(void)
{
	rcc_osc_on(HSI);
	rcc_wait_for_osc_ready(HSI);
	rcc_set_sysclk_source(HSI);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);

	/* 8MHz * 12 / 2 = 24MHz	 */
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16);

	RCC_CFGR &= RCC_CFGR_PLLSRC;

	rcc_osc_on(PLL);
	rcc_wait_for_osc_ready(PLL);
	rcc_set_sysclk_source(PLL);

	rcc_ppre_frequency = 48000000;
	rcc_core_frequency = 48000000;
}

Example #6

File: rcc.c Project: ChenXuJasper/libopencm3

void rcc_clock_setup_in_hsi_out_40mhz(void)
{
	rcc_osc_on(RCC_HSI);
	rcc_wait_for_osc_ready(RCC_HSI);
	rcc_set_sysclk_source(RCC_HSI);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);

	/* 8MHz * 10 / 2 = 40MHz */
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10);

	RCC_CFGR &= ~RCC_CFGR_PLLSRC;

	rcc_osc_on(RCC_PLL);
	rcc_wait_for_osc_ready(RCC_PLL);
	rcc_set_sysclk_source(RCC_PLL);

	rcc_apb1_frequency = 40000000;
	rcc_ahb_frequency = 40000000;
}

Example #7

File: rcc.c Project: esden/libopencm3

void rcc_clock_setup_in_hsi_out_16mhz(void)
{
	rcc_osc_on(HSI);
	rcc_wait_for_osc_ready(HSI);
	rcc_set_sysclk_source(HSI);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);

	/* 8MHz * 4 / 2 = 16MHz	 */
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4);

	RCC_CFGR &= ~RCC_CFGR_PLLSRC;

	rcc_osc_on(PLL);
	rcc_wait_for_osc_ready(PLL);
	rcc_set_sysclk_source(PLL);

	rcc_apb1_frequency = 16000000;
	rcc_ahb_frequency = 16000000;
}

Example #8

File: rcc.c Project: rgwan/libopencm3

/**
 * Set System Clock PLL at 48MHz from HSI
 */
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
	rcc_osc_on(RCC_HSI);
	rcc_wait_for_osc_ready(RCC_HSI);
	rcc_set_sysclk_source(RCC_HSI);

	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);

	flash_prefetch_enable();
	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);

	/* 8MHz * 12 / 2 = 48MHz */
	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
	rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);

	rcc_osc_on(RCC_PLL);
	rcc_wait_for_osc_ready(RCC_PLL);
	rcc_set_sysclk_source(RCC_PLL);

	rcc_apb1_frequency = 48000000;
	rcc_ahb_frequency = 48000000;
}