void RFM70::enableRxPipe(uint8_t pipe_nr) {
uint8_t nr = pipe_nr - 1;
if (nr > 5) {
return;
}
uint8_t tmp;
// set Enable pipe bit
tmp = readRegVal(RFM70_REG_EN_RXADDR);
tmp |= 1 << nr;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_EN_RXADDR, tmp);
}
void RFM70::configCRC(uint8_t crc) {
uint8_t tmp = readRegVal(RFM70_REG_CONFIG);
//reset crc state
tmp &= 0xF3;
if (crc == CRC1) {
tmp |= 0x08;
} else if (crc == CRC2) {
tmp |= 0x0C;
}
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_CONFIG, tmp);
}
void RFM70::setModeRX(void) {
uint8_t val;
// Flush RX FIFO
spiSend(0, (uint8_t *) RFM70_cmd_flush_rx, NELEMS(RFM70_cmd_flush_rx));
// Read Status
val = readRegVal(RFM70_REG_STATUS);
// Reset IRQ bits
uint8_t data[] = {RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, val};
spiSend(0, data, 2);
// RFM chip disable
digitalWrite(_ce, LOW);
// set PRIM_RX bit to 1
val = readRegVal(RFM70_REG_CONFIG);
val |= RFM70_PIN_PRIM_RX;
data[0] = RFM70_CMD_WRITE_REG | RFM70_REG_CONFIG;
data[1] = val;
spiSend(0, data, 2);
// RFM chip enable
digitalWrite(_ce, HIGH);
}
uint8_t RFM70::receivePayload(uint8_t *payload) {
uint8_t len;
// check RX_FIFO
uint8_t status;
status = readRegVal(RFM70_REG_STATUS);
// RX_DR
if (status & RFM70_IRQ_STATUS_RX_DR) {
uint8_t fifo_sta;
// Payload width
len = readRegVal(RFM70_CMD_RX_PL_WID);
readRegBuf(RFM70_CMD_RD_RX_PLOAD, payload, len);
fifo_sta = readRegVal(RFM70_REG_FIFO_STATUS);
if (fifo_sta & RFM70_FIFO_STATUS_RX_EMPTY) {
// clear status bit rx_dr
status |= 0x40 & 0xCF;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, status);
}
return len;
} else {
return 0;
}
}
void RFM70::setModeTX(void) {
uint8_t val;
// Flush TX FIFO
writeRegPgmBuf((uint8_t *) RFM70_cmd_flush_tx, sizeof(RFM70_cmd_flush_tx));
// RFM chip disable
digitalWrite(_ce, LOW);
// set PRIM_RX bit to 0
val = readRegVal(RFM70_REG_CONFIG);
val &= ~RFM70_PIN_PRIM_RX;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_CONFIG, val);
// RFM chip enable
digitalWrite(_ce, HIGH);
}
void RFM70::selectBank(uint8_t bank) {
uint8_t tmp = readRegVal(0x07) & 0x80;
if (bank) {
if (!tmp) {
spiSend(0, (uint8_t *) RFM70_cmd_switch_cfg,
NELEMS(RFM70_cmd_switch_cfg));
}
} else {
if (tmp) {
spiSend(0, (uint8_t *) RFM70_cmd_switch_cfg,
NELEMS(RFM70_cmd_switch_cfg));
}
}
}
void selectBank(uint8_t bank)
{
uint8_t tmp = readRegVal(0x07) & 0x80;
if (bank)
{
if (!tmp)
writeRegPgmBuf((uint8_t *)RFM73_cmd_switch_cfg, sizeof(RFM73_cmd_switch_cfg));
}
else
{
if (tmp)
writeRegPgmBuf((uint8_t *)RFM73_cmd_switch_cfg, sizeof(RFM73_cmd_switch_cfg));
}
}
TransmitResult_t RFM75_Transmit_bytes(const uint8_t *buff,
const uint32_t *length,
const uint32_t maxTimeoutUs,
bool requestAck)
{
TransmitResult_t result;
const uint32_t toSendLength = *length;
uint32_t i=0;
uint8_t status = 0;
bool readStatus = true;
sendPayload(buff, toSendLength, (uint8_t)requestAck);
rxtx_interrupt = 0;
while((rxtx_interrupt == 0) &&
(i < maxTimeoutUs)){
_delay_us(20);
if(checkStatusForMissingIRQ(&status)){
readStatus=false;
break;
}
i++;
}
rxtx_interrupt = 0;
/* Clear the status interrupt */
writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_STATUS, status);
if (readStatus){
status = readRegVal(RFM7x_REG_STATUS);
}
if (status & RFM7x_IRQ_STATUS_TX_DS){
result.status = SUCCESS;
result.bytesSent = toSendLength;
}
else if (status & RFM7x_IRQ_STATUS_MAX_RT){
result.status = MAXRT;
result.bytesSent = 0;
}
else if (status & RFM7x_IRQ_STATUS_TX_FULL){
result.status = FIFOFULL;
result.bytesSent = 0;
}
if (i >= maxTimeoutUs){
result.status = UNKNOWN;
result.bytesSent = 0;
}
return result;
}
void configTxPipe(uint8_t * adr, uint8_t pltype)
{
// write TX address
writeRegCmdBuf(RFM73_CMD_WRITE_REG | RFM73_REG_TX_ADDR, adr, 5);
// write RX0 address
writeRegCmdBuf(RFM73_CMD_WRITE_REG | RFM73_REG_RX_ADDR_P0, adr, 5);
// set static or dynamic payload
uint8_t tmp;
tmp = readRegVal(RFM73_REG_DYNPD);
if (pltype == TX_DPL) // dynamic
tmp |= 1;
else
tmp &= ~(1 << 0);
writeRegVal(RFM73_CMD_WRITE_REG | RFM73_REG_DYNPD, tmp);
}
void RFM70::setModeTX(void) {
uint8_t val;
// Flush TX FIFO
// Maybe we need to do a _cs low
spiSend(0, (uint8_t *) RFM70_cmd_flush_tx, NELEMS(RFM70_cmd_flush_tx));
// RFM chip disable
digitalWrite(_ce, LOW);
// set PRIM_RX bit to 0
val = readRegVal(RFM70_REG_CONFIG);
val &= ~RFM70_PIN_PRIM_RX;
uint8_t data[] = {RFM70_CMD_WRITE_REG | RFM70_REG_CONFIG, val };
spiSend(0, data, 2);
// RFM chip enable
digitalWrite(_ce, HIGH);
}
void RFM70::confIRQ(uint8_t irq_pin, uint8_t reflectTX_DS, uint8_t reflectRX_DR,
uint8_t reflectMAX_RT) {
if (irq_pin != -1) {
pinMode(irq_pin, INPUT);
}
uint8_t tmp = readRegVal(RFM70_REG_CONFIG) & 0x8F;
#if 0
tmp |= ((reflectTX_DS & 0x01) ^ 0x01) << 6;
tmp |= ((reflectRX_DR & 0x01) ^ 0x01) << 5;
tmp |= ((reflectMAX_RT & 0x01) ^ 0x01) << 4;
#else
tmp |= ((reflectTX_DS & 0x01) ^ 0x01) << 5;
tmp |= ((reflectRX_DR & 0x01) ^ 0x01) << 6;
tmp |= ((reflectMAX_RT & 0x01) ^ 0x01) << 4;
#endif
uint8_t data[] = { RFM70_CMD_WRITE_REG | RFM70_REG_CONFIG, tmp };
spiSend(0, data, 2);
}
uint8_t RFM70::rxFIFOEmpty() {
return readRegVal(RFM70_REG_FIFO_STATUS) & RFM70_FIFO_STATUS_RX_EMPTY;
}
uint8_t RFM70::rxFIFOFull() {
return readRegVal(RFM70_REG_FIFO_STATUS) & RFM70_FIFO_STATUS_RX_FULL;
}
uint8_t RFM70::txTimeout() {
return readRegVal(RFM70_REG_STATUS) & RFM70_IRQ_STATUS_MAX_RT;
}
uint8_t RFM70::txDataSent() {
return readRegVal(RFM70_REG_STATUS) & RFM70_IRQ_STATUS_TX_DS;
}
void RFM70::cliAll() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x70;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp);
}
uint8_t getChannel(void)
{
return readRegVal(RFM73_REG_RF_CH);
}
uint8_t RFM70::getChannel(void) {
return readRegVal(RFM70_REG_RF_CH);
}
void RFM70::cliRxDr() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x40 & 0xCF;
uint8_t data[] = { RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp };
spiSend(0, data, 2);
}
void turnOn()
{
uint8_t status = readRegVal(RFM73_REG_STATUS);
status |= PWR_BIT;
writeRegVal(RFM73_CMD_WRITE_REG | RFM73_REG_STATUS, status);
}
void RFM70::cliTimeout() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x10 & 0x9F;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp);
}
void RFM70::cliTxDs() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x20 & 0xAF;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp);
}
void RFM70::cliRxDr() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x40 & 0xCF;
writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp);
}
uint8_t RFM70::getARC(void) {
return readRegVal(RFM70_REG_OBSERVE_TX) & 0x0F;
}
uint8_t getMode(void)
{
return readRegVal(RFM73_REG_CONFIG) & RFM73_PIN_PRIM_RX;
}
uint8_t RFM70::rxDataReceived() {
uint8_t status = readRegVal(RFM70_REG_STATUS);
if (status & RFM70_IRQ_STATUS_RX_DR) {
return ((status & 0x0E) >> 1) + 1;
}
}
uint8_t RFM70::getMode(void) {
return readRegVal(RFM70_REG_CONFIG) & RFM70_PIN_PRIM_RX;
}
void RFM70::cliTimeout() {
uint8_t tmp = readRegVal(RFM70_REG_STATUS) | 0x10 & 0x9F;
uint8_t data[] = {RFM70_CMD_WRITE_REG | RFM70_REG_STATUS, tmp};
spiSend(0, data, 2);
}
bool checkStatusForMissingIRQ(uint8_t &status)
{
status = readRegVal(RFM73_REG_STATUS);
return status != 14;
}
uint8_t RFM70::getCarrierDetect(void) {
return readRegVal(RFM70_REG_CD);
}
