int arch_vcpu_regs_init(struct vmm_vcpu *vcpu)
{
vmm_memset(mips_uregs(vcpu), 0, sizeof(arch_regs_t));
if (!vcpu->is_normal) {
/* For orphan vcpu */
mips_uregs(vcpu)->cp0_epc = vcpu->start_pc;
mips_uregs(vcpu)->regs[SP_IDX] = vcpu->start_sp;
mips_uregs(vcpu)->regs[S8_IDX] = mips_uregs(vcpu)->regs[SP_IDX];
mips_uregs(vcpu)->cp0_status = read_c0_status();
mips_uregs(vcpu)->cp0_entryhi = read_c0_entryhi();
} else {
/* For normal vcpu running guests */
mips_sregs(vcpu)->cp0_regs[CP0_CAUSE_IDX] = 0x400;
mips_sregs(vcpu)->cp0_regs[CP0_STATUS_IDX] = 0x40004;
mips_uregs(vcpu)->cp0_status = read_c0_status() | (0x01UL << CP0_STATUS_UM_SHIFT);
mips_uregs(vcpu)->cp0_entryhi = read_c0_entryhi();
mips_uregs(vcpu)->cp0_entryhi &= ASID_MASK;
mips_uregs(vcpu)->cp0_entryhi |= (0x2 << ASID_SHIFT);
mips_uregs(vcpu)->cp0_epc = vcpu->start_pc;
/* All guest run from 0 and fault */
mips_sregs(vcpu)->cp0_regs[CP0_EPC_IDX] = vcpu->start_pc;
/* Give guest the same CPU cap as we have */
mips_sregs(vcpu)->cp0_regs[CP0_PRID_IDX] = read_c0_prid();
}
return VMM_OK;
}
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
unsigned int prid = read_c0_prid() & 0xffff00;
unsigned int count;
#ifndef CONFIG_CPU_CLOCK
unsigned int ratio;
count = get_sys_mpll(_CPU_PLL_OFFSET);
ratio = 4 - MIPS_CLK_SEL;
count /= ratio;
count *= 500;
#else
count = CONFIG_CPU_CLOCK*500; /*unit of CONFIG_CPU_CLOCK is KHz*/
#endif
mips_hpt_frequency = count;
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
count *= 2;
count += 5000; /* round */
count -= count%10000;
return count;
}
static int __init au1x_pci_setup(void)
{
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
if (!virt_io_addr) {
printk(KERN_ERR "Unable to ioremap pci space\n");
return 1;
}
#ifdef CONFIG_DMA_NONCOHERENT
{
/*
* Set the NC bit in controller for Au1500 pre-AC silicon
*/
u32 prid = read_c0_prid();
if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk("Non-coherent PCI accesses enabled\n");
}
}
#endif
set_io_port_base(virt_io_addr);
#endif
register_pci_controller(&au1x_controller);
return 0;
}
void __init mips_time_init(void)
{
unsigned long flags;
unsigned int est_freq;
local_irq_save(flags);
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08x(%d)\n", r4k_offset, r4k_offset);
if ((read_c0_prid() & 0xffff00) ==
(PRID_COMP_MIPS | PRID_IMP_20KC))
est_freq = r4k_offset*HZ;
else
est_freq = 2*r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
local_irq_restore(flags);
}
static int
tx4939_proc_show_cp0(char *sysbuf, char **start, off_t off,
int count, int *eof, void *data)
{
int len = 0;
len += sprintf(sysbuf + len, "INDEX :0x%08x\n", read_c0_index());
len += sprintf(sysbuf + len, "ENTRYLO0:0x%08lx\n", read_c0_entrylo0());
len += sprintf(sysbuf + len, "ENTRYLO1:0x%08lx\n", read_c0_entrylo1());
len += sprintf(sysbuf + len, "CONTEXT :0x%08lx\n", read_c0_context());
len += sprintf(sysbuf + len, "PAGEMASK:0x%08x\n", read_c0_pagemask());
len += sprintf(sysbuf + len, "WIRED :0x%08x\n", read_c0_wired());
len += sprintf(sysbuf + len, "COUNT :0x%08x\n", read_c0_count());
len += sprintf(sysbuf + len, "ENTRYHI :0x%08lx\n", read_c0_entryhi());
len += sprintf(sysbuf + len, "COMPARE :0x%08x\n", read_c0_compare());
len += sprintf(sysbuf + len, "STATUS :0x%08x\n", read_c0_status());
len += sprintf(sysbuf + len, "CAUSE :0x%08x\n", read_c0_cause());
len += sprintf(sysbuf + len, "PRId :0x%08x\n", read_c0_prid());
len += sprintf(sysbuf + len, "CONFIG :0x%08x\n", read_c0_config());
len += sprintf(sysbuf + len, "XCONTEXT:0x%08lx\n", read_c0_xcontext());
len += sprintf(sysbuf + len, "TagLo :0x%08x\n", read_c0_taglo());
len += sprintf(sysbuf + len, "TagHi :0x%08x\n", read_c0_taghi());
len += sprintf(sysbuf + len, "ErrorEPC:0x%08lx\n", read_c0_errorepc());
*eof = 1;
return len;
}
void __init plat_time_init(void)
{
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
unsigned int freq;
init_rtc();
estimate_frequencies();
freq = mips_hpt_frequency;
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
freq *= 2;
freq = freqround(freq, 5000);
printk("CPU frequency %d.%02d MHz\n", freq/1000000,
(freq%1000000)*100/1000000);
mips_scroll_message();
#ifdef CONFIG_I8253
/* Only Malta has a PIT. */
setup_pit_timer();
#endif
#ifdef CONFIG_MIPS_GIC
if (gic_present) {
freq = freqround(gic_frequency, 5000);
printk("GIC frequency %d.%02d MHz\n", freq/1000000,
(freq%1000000)*100/1000000);
#ifdef CONFIG_CLKSRC_MIPS_GIC
gic_clocksource_init(gic_frequency);
#endif
}
#endif
}
void __cpuinit cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->processor_id = PRID_IMP_UNKNOWN;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX;
c->tlbsize = cpu_tlb_entry; /* defined in bspcpu.h */
c->processor_id = read_c0_prid();
}
static int __init nlm_ahci_init(void)
{
int node = 0;
int chip = read_c0_prid() & PRID_REV_MASK;
if (chip == PRID_IMP_NETLOGIC_XLP3XX)
nlm_sata_firmware_init(node);
return 0;
}
/**
* usb_ohci_au1xxx_probe - initialize Au1xxx-based HCDs
* Context: !in_interrupt()
*
* Allocates basic resources for this USB host controller, and
* then invokes the start() method for the HCD associated with it
* through the hotplug entry's driver_data.
*
*/
static int usb_ohci_au1xxx_probe(const struct hc_driver *driver,
struct platform_device *dev)
{
int retval;
struct usb_hcd *hcd;
#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT)
/* Au1200 AB USB does not support coherent memory */
if (!(read_c0_prid() & 0xff)) {
pr_info("%s: this is chip revision AB !!\n",
dev->name);
pr_info("%s: update your board or re-configure the kernel\n",
dev->name);
return -ENODEV;
}
#endif
if (dev->resource[1].flags != IORESOURCE_IRQ) {
pr_debug("resource[1] is not IORESOURCE_IRQ\n");
return -ENOMEM;
}
hcd = usb_create_hcd(driver, &dev->dev, "au1xxx");
if (!hcd)
return -ENOMEM;
hcd->rsrc_start = dev->resource[0].start;
hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
pr_debug("request_mem_region failed\n");
retval = -EBUSY;
goto err1;
}
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
if (!hcd->regs) {
pr_debug("ioremap failed\n");
retval = -ENOMEM;
goto err2;
}
au1xxx_start_ohc(dev);
ohci_hcd_init(hcd_to_ohci(hcd));
retval = usb_add_hcd(hcd, dev->resource[1].start, IRQF_DISABLED | IRQF_SHARED);
if (retval == 0)
return retval;
au1xxx_stop_ohc(dev);
iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err1:
usb_put_hcd(hcd);
return retval;
}
int checkboard(void)
{
u32 config0 = read_c0_prid();
char *s = getenv("serial#");
if ((config0 & 0xff0000) == PRID_COMP_LEGACY
&& (config0 & 0xff00) == PRID_IMP_LX4280) {
puts("Board: MDED \n");
printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
(config0 >> 8) & 0xFF, config0 & 0xFF);
} else if ((config0 & 0xff0000) == PRID_COMP_MIPS
void
set_cpuspec(void)
{
struct cpu_spec *sp;
u32 prid;
prid = read_c0_prid();
sp = cpu_specs;
while ((prid & sp->prid_mask) != sp->prid_value)
sp++;
cur_cpu_spec[0] = sp;
}
static inline int au1200_coherency_bug(void)
{
#if defined(CONFIG_DMA_COHERENT)
/* */
if (!(read_c0_prid() & 0xff)) {
printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
printk(KERN_INFO "Au1200 USB: update your board or re-configure"
" the kernel\n");
return -ENODEV;
}
#endif
return 0;
}
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
unsigned int prid = read_c0_prid() & 0xffff00;
unsigned int count;
#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
/*
* The SEAD board doesn't have a real time clock, so we can't
* really calculate the timer frequency
* For now we hardwire the SEAD board frequency to 12MHz.
*/
if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
count = 12000000;
else
count = 6000000;
#endif
#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
unsigned long flags;
unsigned int start;
local_irq_save(flags);
/* Start counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
start = read_c0_count();
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count() - start;
/* restore interrupts */
local_irq_restore(flags);
#endif
mips_hpt_frequency = count;
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
count *= 2;
count += 5000; /* round */
count -= count%10000;
return count;
}
void __cpuinit cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
#if defined(CONFIG_CPU_HAS_WATCH)
c->options |= MIPS_CPU_WATCH;
rlx_probe_watch_registers(c);
c->watch_reg_use_cnt = c->watch_reg_count / 2;
#endif
c->processor_id = PRID_IMP_UNKNOWN;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX;
c->tlbsize = cpu_tlb_entry; /* defined in bspcpu.h */
c->processor_id = read_c0_prid();
}
int checkboard(void)
{
u32 proc_id;
u32 config1;
proc_id = read_c0_prid();
printf("Board: Qemu -M mips CPU: ");
switch (proc_id) {
case 0x00018000:
printf("4Kc");
break;
case 0x00018400:
printf("4KEcR1");
break;
case 0x00019000:
printf("4KEc");
break;
case 0x00019300:
config1 = read_c0_config1();
if (config1 & 1)
printf("24Kf");
else
printf("24Kc");
break;
case 0x00019500:
printf("34Kf");
break;
case 0x00000400:
printf("R4000");
break;
case 0x00018100:
config1 = read_c0_config1();
if (config1 & 1)
printf("5Kf");
else
printf("5Kc");
break;
case 0x000182a0:
printf("20Kc");
break;
default:
printf("unknown");
}
printf(" proc_id=0x%x\n", proc_id);
return 0;
}
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
unsigned int prid = read_c0_prid() & 0xffff00;
unsigned int count;
#if 1
/*
* hardwire the board frequency to 12MHz.
*/
if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
count = 12000000;
else
count = 6000000;
#else
unsigned int flags;
local_irq_save(flags);
/* Start counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
write_c0_count(0);
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count();
/* restore interrupts */
local_irq_restore(flags);
#endif
mips_hpt_frequency = count;
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
count *= 2;
count += 5000; /* round */
count -= count%10000;
return count;
}
static void show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
unsigned int cause = regs->cp0_cause;
unsigned int exccode;
int i;
/*
* Saved main processor registers
*/
for (i = 0; i < 32; ) {
if ((i % 4) == 0)
printf("$%2d :", i);
if (i == 0)
printf(" %0*lx", field, 0UL);
else if (i == 26 || i == 27)
printf(" %*s", field, "");
else
printf(" %0*lx", field, regs->regs[i]);
i++;
if ((i % 4) == 0)
puts("\n");
}
printf("Hi : %0*lx\n", field, regs->hi);
printf("Lo : %0*lx\n", field, regs->lo);
/*
* Saved cp0 registers
*/
printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
field, regs->cp0_epc - gd->reloc_off);
printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
field, regs->regs[31] - gd->reloc_off);
printf("Status: %08x\n", (uint32_t) regs->cp0_status);
exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
if (1 <= exccode && exccode <= 5)
printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
printf("PrId : %08x\n", read_c0_prid());
}
/*
* IRIX maps a page at 0x200000 that holds information about the
* process and the system, here we map the page and fill the
* structure
*/
void irix_map_prda_page (void)
{
unsigned long v;
struct prda *pp;
v = do_brk (PRDA_ADDRESS, PAGE_SIZE);
if (v < 0)
return;
pp = (struct prda *) v;
pp->prda_sys.t_pid = current->pid;
pp->prda_sys.t_prid = read_c0_prid();
pp->prda_sys.t_rpid = current->pid;
/* We leave the rest set to zero */
}
/*
* Read CPU type and put its name into buffer
* For now only 24/74Kc are supported as all
* supported SOCs are based on one of them
*/
void cpu_name(char *name)
{
u32 cpu_id = read_c0_prid();
if (name == NULL)
return;
switch (cpu_id & PRID_IMP_MASK) {
case PRID_IMP_24K:
sprintf(name, "MIPS 24Kc");
break;
case PRID_IMP_74K:
sprintf(name, "MIPS 74Kc");
break;
default:
sprintf(name, "MIPS Unknown");
break;
}
}
void __init prom_init(void)
{
extern int tx4927_get_mem_size(void);
extern char* toshiba_name;
int msize;
prom_init_cmdline();
if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) {
mips_machtype = MACH_TOSHIBA_RBTX4927;
toshiba_name = "TX4927";
} else {
mips_machtype = MACH_TOSHIBA_RBTX4937;
toshiba_name = "TX4937";
}
msize = tx4927_get_mem_size();
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
}
PUBLIC
void
Jdb_kern_info_cpu::dump_cp0_regs()
{
Mword val;
DUMP_CP0("EBase", read_c0_ebase(), val);
DUMP_INT("Ebase.CPUNum", (val & 0x3ff));
DUMP_CP0("EntryHi", read_c0_entryhi(), val);
DUMP_HEX("EntryHi.ASID", (val & 0xff));
DUMP_CP0("EPC", read_c0_epc(), val);
DUMP_CP0("Status", read_c0_status(), val);
DUMP_CP0("Cause", read_c0_cause(), val);
DUMP_CP0("PRId", read_c0_prid(), val);
DUMP_CP0("HWREna", read_c0_hwrena(), val);
DUMP_CP0("Config", read_c0_config(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config1", read_c0_config1(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config2", read_c0_config2(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config3", read_c0_config3(), val);
if (val & MIPS_CONF3_ULRI)
DUMP_CP0("UserLocal", read_c0_userlocal(), val);
}
}
}
if (cpu_has_vz)
DUMP_CP0("GuestCtl0", read_c0_guestctl0(), val);
if (cpu_has_guestctl0ext)
DUMP_CP0("GuestCtl0Ext", read_c0_guestctl0ext(), val);
if (cpu_has_vz)
DUMP_CP0("GTOffset", read_c0_gtoffset(), val);
if (cpu_has_guestctl1) {
DUMP_CP0("GuestCtl1", read_c0_guestctl1(), val);
DUMP_HEX("GuestCtl1.ID", (val & GUESTCTL1_ID));
}
if (cpu_has_guestctl2) {
DUMP_CP0("GuestCtl2", read_c0_guestctl2(), val);
DUMP_HEX("GuestCtl2.VIP", (val & GUESTCTL2_VIP));
}
}
/*
* IRIX maps a page at 0x200000 that holds information about the
* process and the system, here we map the page and fill the
* structure
*/
static void irix_map_prda_page(void)
{
unsigned long v;
struct prda *pp;
down_write(¤t->mm->mmap_sem);
v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
up_write(¤t->mm->mmap_sem);
if (v < 0)
return;
pp = (struct prda *) v;
pp->prda_sys.t_pid = task_pid_vnr(current);
pp->prda_sys.t_prid = read_c0_prid();
pp->prda_sys.t_rpid = task_pid_vnr(current);
/* We leave the rest set to zero */
}
void __init plat_mem_setup(void)
{
struct cpu_spec *sp;
char *argptr;
unsigned long prid, cpufreq, bclk = 1;
set_cpuspec();
sp = cur_cpu_spec[0];
board_setup(); /* board specific setup */
prid = read_c0_prid();
if (sp->cpu_pll_wo)
#ifdef CONFIG_SOC_AU1000_FREQUENCY
cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
#else
cpufreq = 396;
#endif
else
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
*/
static unsigned int __init estimate_cpu_frequency(void)
{
unsigned int prid = read_c0_prid() & 0xffff00;
unsigned int tick = 0;
unsigned int freq;
unsigned int orig;
unsigned long flags;
local_irq_save(flags);
orig = readl(status_reg) & 0x2; /* get original sample */
/* wait for transition */
while ((readl(status_reg) & 0x2) == orig)
;
orig = orig ^ 0x2; /* flip the bit */
write_c0_count(0);
/* wait 1 second (the sampling clock transitions every 10ms) */
while (tick < 100) {
/* wait for transition */
while ((readl(status_reg) & 0x2) == orig)
;
orig = orig ^ 0x2; /* flip the bit */
tick++;
}
freq = read_c0_count();
local_irq_restore(flags);
mips_hpt_frequency = freq;
/* Adjust for processor */
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
freq *= 2;
freq += 5000; /* rounding */
freq -= freq%10000;
return freq ;
}
void __init prom_init(void)
{
const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES;
extern int tx4927_get_mem_size(void);
extern char* toshiba_name;
int msize;
prom_init_cmdline();
mips_machgroup = MACH_GROUP_TOSHIBA;
if ((read_c0_prid() & 0xff) == PRID_REV_TX4927)
mips_machtype = MACH_TOSHIBA_RBTX4927;
else
mips_machtype = MACH_TOSHIBA_RBTX4937;
toshiba_name = toshiba_name_list[mips_machtype];
msize = tx4927_get_mem_size();
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
}
__init void cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
c->cputype = CPU_UNKNOWN;
/* add by rupert*/
c->cputype = CPU_R3000;
c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB;
c->tlbsize = 16;
return;
c->processor_id = read_c0_prid();
switch (c->processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
cpu_probe_legacy(c);
break;
case PRID_COMP_MIPS:
cpu_probe_mips(c);
break;
case PRID_COMP_ALCHEMY:
cpu_probe_alchemy(c);
break;
case PRID_COMP_SIBYTE:
cpu_probe_sibyte(c);
break;
case PRID_COMP_SANDCRAFT:
cpu_probe_sandcraft(c);
break;
default:
c->cputype = CPU_UNKNOWN;
}
if (c->options & MIPS_CPU_FPU)
c->fpu_id = cpu_get_fpu_id();
}
void __init mips_time_init(void)
{
unsigned long flags;
unsigned int est_freq;
local_irq_save(flags);
#ifndef CONFIG_RALINK_EXTERNAL_TIMER
mips_hpt_frequency = mips_cpu_feq/2;
#else
#ifdef CONFIG_RT3352_FPGA
mips_hpt_frequency = 10000000;
#else
mips_hpt_frequency = 40000000;
#endif
#endif
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08x(%d)\n", r4k_offset, r4k_offset);
#if 0
if ((read_c0_prid() & 0xffff00) ==
(PRID_COMP_MIPS | PRID_IMP_20KC))
est_freq = r4k_offset*HZ;
else
est_freq = 2*r4k_offset*HZ;
#endif
est_freq = r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
local_irq_restore(flags);
}
/**
* User is reading /proc/octeon_info
*
* @param m
* @param v
* @return
*/
static int octeon_info_show(struct seq_file *m, void *v)
{
seq_printf(m, "processor_id: 0x%x\n", read_c0_prid());
seq_printf(m, "boot_flags: 0x%x\n", octeon_bootinfo->flags);
seq_printf(m, "dram_size: %u\n", octeon_bootinfo->dram_size);
seq_printf(m, "phy_mem_desc_addr: 0x%x\n",
octeon_bootinfo->phy_mem_desc_addr);
seq_printf(m, "eclock_hz: %u\n", octeon_bootinfo->eclock_hz);
seq_printf(m, "io_clock_hz: %llu\n", octeon_get_io_clock_rate());
seq_printf(m, "dclock_hz: %u\n", octeon_bootinfo->dclock_hz);
seq_printf(m, "board_type: %u\n", octeon_bootinfo->board_type);
seq_printf(m, "board_rev_major: %u\n",
octeon_bootinfo->board_rev_major);
seq_printf(m, "board_rev_minor: %u\n",
octeon_bootinfo->board_rev_minor);
seq_printf(m, "board_serial_number: %s\n",
octeon_bootinfo->board_serial_number);
seq_printf(m, "mac_addr_base: %02x:%02x:%02x:%02x:%02x:%02x\n",
(int) octeon_bootinfo->mac_addr_base[0],
(int) octeon_bootinfo->mac_addr_base[1],
(int) octeon_bootinfo->mac_addr_base[2],
(int) octeon_bootinfo->mac_addr_base[3],
(int) octeon_bootinfo->mac_addr_base[4],
(int) octeon_bootinfo->mac_addr_base[5]);
seq_printf(m, "mac_addr_count: %u\n",
octeon_bootinfo->mac_addr_count);
#if CONFIG_CAVIUM_RESERVE32
seq_printf(m, "32bit_shared_mem_base: 0x%lx\n",
(long int) octeon_reserve32_memory);
seq_printf(m, "32bit_shared_mem_size: 0x%x\n",
(long int) octeon_reserve32_memory ? CONFIG_CAVIUM_RESERVE32 << 20 : 0);
#else
seq_printf(m, "32bit_shared_mem_base: 0x%lx\n", 0ul);
seq_printf(m, "32bit_shared_mem_size: 0x%x\n", 0);
#endif
return 0;
}
__init void cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
c->cputype = CPU_UNKNOWN;
c->processor_id = read_c0_prid();
switch (c->processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
cpu_probe_legacy(c);
break;
case PRID_COMP_MIPS:
cpu_probe_mips(c);
break;
case PRID_COMP_ALCHEMY:
cpu_probe_alchemy(c);
break;
case PRID_COMP_SIBYTE:
cpu_probe_sibyte(c);
break;
#if defined(CONFIG_MIPS_BRCM)
case PRID_COMP_BROADCOM:
cpu_probe_broadcom(c);
break;
#endif
case PRID_COMP_SANDCRAFT:
cpu_probe_sandcraft(c);
break;
default:
c->cputype = CPU_UNKNOWN;
}
if (c->options & MIPS_CPU_FPU)
c->fpu_id = cpu_get_fpu_id();
}
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
unsigned int prid = read_c0_prid() & 0xffff00;
unsigned int count;
unsigned long flags;
unsigned int start;
local_irq_save(flags);
/* Start counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
start = read_c0_count();
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count() - start;
/* restore interrupts */
local_irq_restore(flags);
mips_hpt_frequency = count;
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
count *= 2;
count += 5000; /* round */
count -= count%10000;
return count;
}
