C++ (Cpp) read_c0_tcbind Examples

Example #1

File: smp.c Project: Einheri/wl500g

/*
 * First C code run on the secondary CPUs after being started up by
 * the master.
 */
asmlinkage __cpuinit void start_secondary(void)
{
	unsigned int cpu;

#ifdef CONFIG_MIPS_MT_SMTC
	/* Only do cpu_probe for first TC of CPU */
	if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
#endif /* CONFIG_MIPS_MT_SMTC */
	cpu_probe();
	cpu_report();
	per_cpu_trap_init();
	prom_init_secondary();

	/*
	 * XXX parity protection should be folded in here when it's converted
	 * to an option instead of something based on .cputype
	 */

	calibrate_delay();
	preempt_disable();
	cpu = smp_processor_id();
	cpu_data[cpu].udelay_val = loops_per_jiffy;

	prom_smp_finish();

	cpu_set(cpu, cpu_callin_map);

	cpu_idle();
}

Example #2

File: msp_smtc.c Project: CSCLOG/beaglebone

/*
 * Post-config but pre-boot cleanup entry point
 */
static void __cpuinit msp_smtc_init_secondary(void)
{
	int myvpe;

	/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
	myvpe = read_c0_tcbind() & TCBIND_CURVPE;
	if (myvpe > 0)
		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
				STATUSF_IP6 | STATUSF_IP7);
	smtc_init_secondary();
}

Example #3

File: msp_smtc.c Project: Blackburn29/PsycoKernel

static void __cpuinit msp_smtc_init_secondary(void)
{
	int myvpe;

	
	myvpe = read_c0_tcbind() & TCBIND_CURVPE;
	if (myvpe > 0)
		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
				STATUSF_IP6 | STATUSF_IP7);
	smtc_init_secondary();
}

Example #4

File: malta-smtc.c Project: 08opt/linux

/*
 * Post-config but pre-boot cleanup entry point
 */
static void __cpuinit msmtc_init_secondary(void)
{
	int myvpe;

	/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
	myvpe = read_c0_tcbind() & TCBIND_CURVPE;
	if (myvpe != 0) {
		/* Ideally, this should be done only once per VPE, but... */
		clear_c0_status(ST0_IM);
		set_c0_status((0x100 << cp0_compare_irq)
				| (0x100 << MIPS_CPU_IPI_IRQ));
		if (cp0_perfcount_irq >= 0)
			set_c0_status(0x100 << cp0_perfcount_irq);
	}

	smtc_init_secondary();
}

Example #5

File: malta_smtc.c Project: ndmsystems/linux-2.6.22-tc

void prom_init_secondary(void)
{
        void smtc_init_secondary(void);
	int myvpe;

	/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
	myvpe = read_c0_tcbind() & TCBIND_CURVPE;
	if (myvpe != 0) {
		/* Ideally, this should be done only once per VPE, but... */
		clear_c0_status(STATUSF_IP2);
		set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3
				| STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6
				| STATUSF_IP7);
	}

        smtc_init_secondary();
}

Example #6

File: malta-smtc.c Project: romanbb/android_kernel_lge_d851

static void __cpuinit msmtc_init_secondary(void)
{
	int myvpe;

	/*                                                            */
	myvpe = read_c0_tcbind() & TCBIND_CURVPE;
	if (myvpe != 0) {
		/*                                                        */
		clear_c0_status(ST0_IM);
		set_c0_status((0x100 << cp0_compare_irq)
				| (0x100 << MIPS_CPU_IPI_IRQ));
		if (cp0_perfcount_irq >= 0)
			set_c0_status(0x100 << cp0_perfcount_irq);
	}

	smtc_init_secondary();
}