void do_activation_estimation(
int num_types,
t_type_descriptor * type_descriptors)
{
netlist_t *blif_netlist;
netlist_t *net_netlist;
int lut_size;
if ((global_args.activation_blif_file == NULL) || (global_args.activation_netlist_file == NULL) || (global_args.arch_file == NULL))
{
return;
}
lut_size = type_descriptors[2].max_subblock_inputs;
printf("--------------------------------------------------------------------\n");
printf("Activation Estimation Begin\n");
/* read in the blif file */
printf("Reading blif format in for probability densitity estimation\n");
read_blif (global_args.activation_blif_file);
blif_netlist = verilog_netlist;
/* read in the blif file */
/* IO type is known from read_arch library #define EMPTY_TYPE_INDEX 0 #define IO_TYPE_INDEX 1 */
printf("Reading netlist format in for probability densitity estimation\n");
net_netlist = read_netlist (global_args.activation_netlist_file, num_types, type_descriptors, &type_descriptors[1]);
/* do activation estimation */
activity_estimation(NULL, global_args.output_file, lut_size, blif_netlist, net_netlist);
free_netlist(blif_netlist);
free_netlist(net_netlist);
printf("Successful Activation Estimation \n");
printf("--------------------------------------------------------------------\n");
}
/*
* Sets globals: nx, ny
* Allocs globals: chan_width_x, chan_width_y, grid
* Depends on num_clbs, pins_per_clb */
void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
int *num_instances_type, *num_blocks_type;
int i;
int current, high, low;
boolean fit;
/* Read in netlist file for placement and routing */
if (vpr_setup.FileNameOpts.NetFile) {
read_netlist(vpr_setup.FileNameOpts.NetFile, &Arch, &num_blocks, &block,
&num_nets, &clb_net);
/* This is done so that all blocks have subblocks and can be treated the same */
check_netlist();
}
/* Output the current settings to console. */
printClusteredNetlistStats();
if (vpr_setup.Operation == TIMING_ANALYSIS_ONLY) {
do_constant_net_delay_timing_analysis(vpr_setup.Timing,
vpr_setup.constant_net_delay);
} else {
current = nint((float)sqrt((float)num_blocks)); /* current is the value of the smaller side of the FPGA */
low = 1;
high = -1;
num_instances_type = (int*) my_calloc(num_types, sizeof(int));
num_blocks_type = (int*) my_calloc(num_types, sizeof(int));
for (i = 0; i < num_blocks; i++) {
num_blocks_type[block[i].type->index]++;
}
if (Arch.clb_grid.IsAuto) {
/* Auto-size FPGA, perform a binary search */
while (high == -1 || low < high) {
/* Generate grid */
if (Arch.clb_grid.Aspect >= 1.0) {
ny = current;
nx = nint(current * Arch.clb_grid.Aspect);
} else {
nx = current;
ny = nint(current / Arch.clb_grid.Aspect);
}
#if DEBUG
vpr_printf(TIO_MESSAGE_INFO,
"Auto-sizing FPGA at x = %d y = %d\n", nx, ny);
#endif
alloc_and_load_grid(num_instances_type, &Arch);
freeGrid();
/* Test if netlist fits in grid */
fit = TRUE;
for (i = 0; i < num_types; i++) {
if (num_blocks_type[i] > num_instances_type[i]) {
fit = FALSE;
break;
}
}
/* get next value */
if (!fit) {
/* increase size of max */
if (high == -1) {
current = current * 2;
if (current > MAX_SHORT) {
vpr_printf(TIO_MESSAGE_ERROR,
"FPGA required is too large for current architecture settings.\n");
exit(1);
}
} else {
if (low == current)
current++;
low = current;
current = low + ((high - low) / 2);
}
} else {
high = current;
current = low + ((high - low) / 2);
}
}
/* Generate grid */
if (Arch.clb_grid.Aspect >= 1.0) {
ny = current;
nx = nint(current * Arch.clb_grid.Aspect);
} else {
nx = current;
ny = nint(current / Arch.clb_grid.Aspect);
}
alloc_and_load_grid(num_instances_type, &Arch);
vpr_printf(TIO_MESSAGE_INFO, "FPGA auto-sized to x = %d y = %d\n",
nx, ny);
} else {
nx = Arch.clb_grid.W;
ny = Arch.clb_grid.H;
alloc_and_load_grid(num_instances_type, &Arch);
}
vpr_printf(TIO_MESSAGE_INFO,
"The circuit will be mapped into a %d x %d array of clbs.\n",
nx, ny);
/* Test if netlist fits in grid */
fit = TRUE;
for (i = 0; i < num_types; i++) {
if (num_blocks_type[i] > num_instances_type[i]) {
fit = FALSE;
break;
}
}
if (!fit) {
vpr_printf(TIO_MESSAGE_ERROR,
"Not enough physical locations for type %s, number of blocks is %d but number of locations is %d.\n",
type_descriptors[i].name, num_blocks_type[i],
num_instances_type[i]);
exit(1);
}
vpr_printf(TIO_MESSAGE_INFO, "\n");
vpr_printf(TIO_MESSAGE_INFO, "Resource usage...\n");
for (i = 0; i < num_types; i++) {
vpr_printf(TIO_MESSAGE_INFO,
"\tNetlist %d\tblocks of type: %s\n",
num_blocks_type[i], type_descriptors[i].name);
vpr_printf(TIO_MESSAGE_INFO,
"\tArchitecture %d\tblocks of type: %s\n",
num_instances_type[i], type_descriptors[i].name);
}
vpr_printf(TIO_MESSAGE_INFO, "\n");
chan_width_x = (int *) my_malloc((ny + 1) * sizeof(int));
chan_width_y = (int *) my_malloc((nx + 1) * sizeof(int));
free(num_blocks_type);
free(num_instances_type);
}
}
