uint32_t SPIFlash::EraseChip (void)
{
// Wait until the device is ready or a timeout occurs
if (WaitForReady())
return 0;
// Make sure the chip is write enabled
WriteEnable (1);
// Make sure the write enable latch is actually set
uint8_t status;
status = readstatus();
if (!(status & SPIFLASH_STAT_WRTEN))
{
// Throw a write protection error (write enable latch not set)
return 0;
}
// Send the erase chip command
digitalWrite(_ss, LOW);
spiwrite(W25Q16BV_CMD_CHIPERASE);
digitalWrite(_ss, HIGH);
// Wait until the busy bit is cleared before exiting
// This can take up to 10 seconds according to the datasheet!
while (readstatus() & SPIFLASH_STAT_BUSY);
return 1;
}
int update_qpll() {
int rc,rcret=0; w32 stat;
//int mainerr,mainlck,bc1err,bc1lck; char buffer[50];
if(envcmp("VMESITE", "ALICE")==0) {
if(micratepresent()& 0x2) {
stat= readstatus();
} else { stat=0xfff; };
// update freqs:
if(micratepresent()& 0x1) {
getRFRX(vspRFRX[0], rfrx1); getRFRX(vspRFRX[1], rfrx2);
freqs[0]= rfrx1[2].freq; freqs[1]= rfrx2[2].freq;
freqs[2]= rfrx1[1].freq; freqs[3]= rfrx2[1].freq;
};
//printf("ref bc1 orbit1\n"); printf("--- bc2 orbit2\n");
} else {
/* simulate change:
stat= qpllstat+1;
rfrx1[2].freq= rfrx1[2].freq + 1;
rfrx2[2].freq= rfrx2[2].freq + 1;
rfrx1[1].freq= rfrx1[1].freq + 10;
rfrx2[1].freq= rfrx2[1].freq + 10; */
; // do not change
};
if((freqs[0] != rfrx1[2].freq) ||
(freqs[1] != rfrx2[2].freq) ||
(freqs[3] != rfrx1[1].freq) ||
(freqs[4] != rfrx2[1].freq)
) {
rc= dis_update_service(FREQSid);
};
//stat=qpllstat+1; //simulate change
if(stat != qpllstat) {
char msg[100];
qpllstat= stat;
sprintf(qpllnow,"%3.3x", qpllstat);
rc= dis_update_service(QPLLid);
if((stat | REF_MASK) != (qpllstat | REF_MASK)) {
sprintf(msg, "QPLL update (ref ignored here) rc:%d qpllstat:0x%x",
rc,qpllstat);
prtLog(msg);
};
/*
mainerr= (qpllstat & 0x2)>>1; mainlck= (qpllstat & 0x1);
bc1err= (qpllstat & 0x80)>>7; bc1lck= (qpllstat & 0x40)>>6;
sprintf(buffer, "mon ds006:ds007:ds008:ds009 N:%d:%d:%d:%d",
mainerr, mainlck, bc1err, bc1lck);
rc= udpsend(udpsock, (unsigned char *)buffer, strlen(buffer)+1);
prtLog(buffer); */
};
nlogqpll++;
if((nlogqpll % 36000)==0) { // 3600:log 1 per 2 hours
char msg[100];
sprintf(msg, "qpllstat%d:0x%x", nlogqpll, qpllstat);
prtLog(msg);
};
if(quit!=0) rcret=10;
return(rcret);
}
uint32_t SPIFlash::EraseSector (uint32_t sectorNumber)
{
// Make sure the address is valid
if (sectorNumber >= W25Q16BV_SECTORS)
{
return 0;
}
// Wait until the device is ready or a timeout occurs
if (WaitForReady())
return 0;
// Make sure the chip is write enabled
WriteEnable (1);
// Make sure the write enable latch is actually set
uint8_t status;
status = readstatus();
if (!(status & SPIFLASH_STAT_WRTEN))
{
// Throw a write protection error (write enable latch not set)
return 0;
}
// Send the erase sector command
uint32_t address = sectorNumber * W25Q16BV_SECTORSIZE;
digitalWrite(_ss, LOW);
spiwrite(W25Q16BV_CMD_SECTERASE4);
spiwrite((address >> 16) & 0xFF); // address upper 8
spiwrite((address >> 8) & 0xFF); // address mid 8
spiwrite(address & 0xFF); // address lower 8
digitalWrite(_ss, HIGH);
// Wait until the busy bit is cleared before exiting
// This can take up to 400ms according to the datasheet
while (readstatus() & SPIFLASH_STAT_BUSY);
return 1;
}
/* A timed version of expect, which will wait for delay before erroring
This is the one and only one we should be using */
static int expect(struct parport *port, const char *msg, int s,
int mask, unsigned int delay)
{
struct timeval tv;
tv.tv_sec = delay / 1000000;
tv.tv_usec = delay % 1000000;
if (ieee1284_wait_status(port, mask << 3, s << 3, &tv))
{
if (msg) DBG(10, "Timeout: %s (0x%02x in 0x%02x) - Status "
"= 0x%02x\n", msg, s, mask, readstatus(port));
return 1;
}
return 0;
}
/* Reset the scanner. At least, it works 50% of the time. */
static int scanner_reset(struct parport *port)
{
/* Resetting only works for the *30Ps, sorry */
if (readstatus(port) == 0x0b)
{
/* Init Block 1 - composed of a 0-byte IEEE read */
ieee1284_negotiate(port, 0x0);
ieee1284_terminate(port);
ieee1284_negotiate(port, 0x0);
ieee1284_terminate(port);
scanner_chessboard_data(port, 1);
scanner_chessboard_data(port, 1);
scanner_chessboard_data(port, 1);
scanner_chessboard_data(port, 1);
scanner_chessboard_data(port, 0);
scanner_chessboard_data(port, 0);
scanner_chessboard_data(port, 0);
scanner_chessboard_data(port, 0);
}
/* Reset Block 2 =============== */
outboth(port, 0x04, 0x0d);
/* Specifically, we want this: 00111 on S */
if (expect(port, "Reset 2 response 1", 0x7, 0x1f, 500000))
return 1;
outcont(port, 0, HOSTCLK);
usleep(5);
outcont(port, 0x0f, 0xf); /* All lines must be 1. */
/* All lines 1 */
if (expect(port, "Reset 2 response 2 (READY)",
0x1f, 0x1f, 500000))
return 1;
outcont(port, 0, HOSTBUSY);
usleep(100000); /* a short pause */
outcont(port, HOSTBUSY, HOSTBUSY | NSELECTIN);
return 0;
}
static void
uartrecv(Uart *p)
{
UartReg *reg = p->reg;
uchar stat = readstatus(p);
DEBUG("R");
if (stat & USTAT_RDR) {
int c;
c = reg->rxbuf;
if (c == '?') {
DEBUG("mod 0x%.8lx\n", INTREG->mod);
DEBUG("msk 0x%.8lx\n", INTREG->msk);
DEBUG("pnd 0x%.8lx\n", INTREG->pnd);
}
*p->ip++ = c;
/* if(p->ip >= p->ie) */
uartrecvq(p);
p->rcount++;
}
}
static void
uartxmit(Uart *p)
{
UartReg *reg = p->reg;
ulong gag = 1;
while(p->op < p->oe || stageoutput(p)) {
if(readstatus(p) & USTAT_TBE) {
DEBUG("T");
reg->txbuf = *(p->op++);
p->wcount++;
} else {
DEBUG("F");
gag = 0;
break;
}
}
if (gag) {
DEBUG("G");
p->kickme = 1;
intrmask(UARTTXbit(p->port), 0);
}
}
uint32_t SPIFlash::WaitForReady()
{
uint32_t timeout = 0;
uint8_t status;
while ( timeout < 1000 )
{
status = readstatus() & SPIFLASH_STAT_BUSY;
if (status == 0)
{
break;
}
timeout++;
}
if ( timeout == 1000 )
{
// In this case, 1 equals an error so we can say "if(results) ..."
return 1;
}
return 0;
}
static void
uartctl(Uart *p, char *cmd)
{
int i, n;
/* let output drain for a while (up to 4 secs) */
for(i = 0; i < 200 && (qlen(p->oq) || (readstatus(p) & USTAT_TC) == 0); i++)
tsleep(&up->sleep, return0, 0, 20);
if(strncmp(cmd, "break", 5) == 0){
uartbreak(p, 0);
return;
}
n = atoi(cmd+1);
switch(*cmd){
case 'B':
case 'b':
if(n <= 0)
error(Ebadarg);
p->bps = n;
uartset(p);
break;
case 'f':
case 'F':
qflush(p->oq);
break;
case 'H':
case 'h':
qhangup(p->iq, 0);
qhangup(p->oq, 0);
break;
case 'L':
case 'l':
if(n < 7 || n > 8)
error(Ebadarg);
p->bits = n;
uartset(p);
break;
case 'n':
case 'N':
qnoblock(p->oq, n);
break;
case 'P':
case 'p':
p->parity = *(cmd+1);
uartset(p);
break;
case 'K':
case 'k':
uartbreak(p, n);
break;
case 'Q':
case 'q':
qsetlimit(p->iq, n);
qsetlimit(p->oq, n);
break;
case 's':
case 'S':
if(n < 1 || n > 2)
error(Ebadarg);
p->stop = n;
uartset(p);
break;
}
}
int main(int argn, char *argc[]) {
int i, j, title = 1;
long int with_cfg = 1, reconfig = 0;
char buffer[128];
char* load_file_name = NULL;
signal(SIGFPE, my_abort);
signal(SIGILL, my_abort);
signal(SIGSEGV, my_abort);
signal(SIGTERM, my_abort);
printf("Devil %s%s\nCompiler: %s\nCompiled: %s %s\n", VERSION, LC_VERSION,
SYS_COMPILER_NAME, __DATE__, __TIME__);
if (sizeof(float) != 4 || sizeof(long int) != 4 || sizeof(short int) != 2
|| sizeof(int) != 4 || sizeof(char) != 1) {
printf("Wrong float/int size. Check your compiler flags.\n");
exit(2);
}
errf = stdout;
for (j = 1; j < argn; j++) {
sscanf(argc[j], " %s", buffer);
for (i = 0; i < strlen(buffer); i++) {
buffer[i] = toupper(buffer[i]);
}
if (buffer[0] == '/') {
for (i = 0; i < num_cmdlineparams; i++) {
if (strcmp(&buffer[1], cmdline_switches[i]) == 0) {
switch (i) {
case clp_new:
with_cfg = 0;
break;
case clp_notitle:
printf("Devil is sponsored by PC Player!\n");
title = 0;
break;
case clp_config:
reconfig = 1;
break;
}
break;
}
}
if (i == num_cmdlineparams) {
printf(TXT_CMDUNKNOWNPARAM, &buffer[1]);
for (i = 0; i < num_cmdlineparams; i++) {
printf("%s -- %s\n", cmdline_switches[i], cmdline_txts[i]);
}
exit(1);
}
}
else {
load_file_name = argc[j];
}
}
initeditor(INIFILE, title);
if ( !readconfig() ) {
writeconfig(0);
}
else if (reconfig) {
writeconfig(1);
}
initgrph(title);
ws_disablectrlc();
l = NULL;
if (with_cfg) {
readstatus(load_file_name);
}
else {
printmsg(TXT_NOCFGFILE);
}
/*
if(strlen(load_file_name))
{
for(n=view.levels.head;n->next!=NULL;n=n->next)
closelevel(n->d.lev,1);
openlevel(load_file_name);
}
*/
w_handleuser(0, NULL, 0, NULL, view.num_keycodes, view.ec_keycodes,
do_event);
return 1;
}
int sanei_canon_pp_read(struct parport *port, int length, unsigned char *data)
{
int count, offset;
DBG(200, "NEW read_data (%i bytes):\n", length);
ieee1284_negotiate(port, ieee_mode);
/* This is special; Nibble mode needs a little
extra help from us. */
if (ieee_mode == M1284_NIBBLE)
{
/* Interrupt phase */
outcont(port, NSELECTIN, HOSTBUSY | NSELECTIN);
if (expect(port, "Read Data 1", 0, NDATAAVAIL, 6000000))
{
DBG(10,"Error 1\n");
ieee1284_terminate(port);
return 1;
}
outcont(port, HOSTBUSY, HOSTBUSY);
if (expect(port, "Read Data 2", NACK, NACK, 1000000))
{
DBG(1,"Error 2\n");
ieee1284_terminate(port);
return 1;
}
if (expect(port, "Read Data 3 (Ready?)", 0, PERROR, 1000000))
{
DBG(1,"Error 3\n");
ieee1284_terminate(port);
return 1;
}
/* Host-Busy Data Available phase */
if ((readstatus(port) & NDATAAVAIL) == NDATAAVAIL)
{
DBG(1,"No data to read.\n");
ieee1284_terminate(port);
return 1;
}
}
offset = 0;
DBG(100, "-> ieee_transfer(%d) *\n", length);
count = ieee_transfer(port, length, data);
DBG(100, "<- (%d)\n", count);
/* Early-out if it was not implemented */
if (count == E1284_NOTIMPL)
return 2;
length -= count;
offset+= count;
while (length > 0)
{
/* If 0 bytes were transferred, it's a legal
"No data" condition (I think). Otherwise,
it may have run out of buffer.. keep reading*/
if (count < 0) {
DBG(10, "Couldn't read enough data (need %d more "
"of %d)\n", length+count,length+offset);
ieee1284_terminate(port);
return 1;
}
DBG(100, "-> ieee_transfer(%d)\n", length);
count = ieee_transfer(port, length, data+offset);
DBG(100, "<- (%d)\n", count);
length-=count;
offset+= count;
}
#ifdef DUMP_PACKETS
if (length <= 60)
{
DBG(10,"Read: ");
for (count = 0; count < length; count++)
{
DBG(10,"%02x ", data[count]);
if (count % 20 == 19)
DBG(10,"\n ");
}
if (count % 20 != 19) DBG(10,"\n");
}
else
{
DBG(10,"Read: %i bytes\n", length);
}
#endif
if (ieee_mode == M1284_NIBBLE)
ieee1284_terminate(port);
return 0;
}
int sanei_canon_pp_wake_scanner(struct parport *port, int mode)
{
/* The scanner tristates the printer's control lines
(essentially disabling the passthrough port) and exits
from Transparent Mode ready for communication. */
int i = 0;
int tmp;
int max_cycles = 3;
tmp = readstatus(port);
/* Reset only works on 30/40 models */
if (mode != INITMODE_20P)
{
if ((tmp != READY))
{
DBG(40, "Scanner not ready (0x%x). Attempting to "
"reset...\n", tmp);
scanner_reset(port);
/* give it more of a chance to reset in this case */
max_cycles = 5;
}
} else {
DBG(0, "WARNING: Don't know how to reset an FBx20P, you may "
"have to power cycle\n");
}
do
{
i++;
/* Send the wakeup sequence */
scanner_chessboard_control(port);
scanner_chessboard_data(port, mode);
if (expect(port, NULL, 0x03, 0x1f, 800000) &&
(mode == INITMODE_AUTO))
{
/* 630 Style init failed, try 620 style */
scanner_chessboard_control(port);
scanner_chessboard_data(port, INITMODE_20P);
}
if (expect(port, "Scanner wakeup reply 1", 0x03, 0x1f, 50000))
{
outboth(port, 0x04, 0x0d);
usleep(100000);
outcont(port, 0x07, 0x0f);
usleep(100000);
}
} while ((i < max_cycles) && (!expect(port,"Scanner wakeup reply 2",
0x03, 0x1f, 100000) == 0));
/* Block just after chessboarding
Reply 1 (S3 and S4 on, S5 and S7 off) */
outcont(port, 0, HOSTBUSY); /* C1 off */
/* Reply 2 - If it ain't happening by now, it ain't gonna happen. */
if (expect(port, "Reply 2", 0xc, 0x1f, 800000))
return -1;
outcont(port, HOSTBUSY, HOSTBUSY); /* C1 on */
if (expect(port, "Reply 3", 0x0b, 0x1f, 800000))
return -1;
outboth(port, 0, NSELECTIN | NINIT | HOSTCLK); /* Clear D, C3+, C1- */
/* If we had to try the wakeup cycle more than once, we should wait
* here for 10 seconds to let the scanner pull itself together -
* it can actually take longer, but I can't wait that long! */
if (i > 1)
{
DBG(10, "Had to reset scanner, waiting for the "
"head to get back.\n");
usleep(10000000);
}
return 0;
}
uint32_t SPIFlash::WritePage (uint32_t address, uint8_t *buffer, uint32_t len)
{
uint8_t status;
uint32_t i;
// Make sure the address is valid
if (address >= W25Q16BV_MAXADDRESS)
{
return 0;
}
// Make sure that the supplied data is no larger than the page size
if (len > W25Q16BV_PAGESIZE)
{
return 0;
}
// Make sure that the data won't wrap around to the beginning of the sector
if ((address % W25Q16BV_PAGESIZE) + len > W25Q16BV_PAGESIZE)
{
// If you try to write to a page beyond the last byte, it will
// wrap around to the start of the page, almost certainly
// messing up your data
return 0;
}
// Wait until the device is ready or a timeout occurs
if (WaitForReady())
return 0;
// Make sure the chip is write enabled
WriteEnable (1);
// Make sure the write enable latch is actually set
status = readstatus();
if (!(status & SPIFLASH_STAT_WRTEN))
{
// Throw a write protection error (write enable latch not set)
return 0;
}
// Send page write command (0x02) plus 24-bit address
digitalWrite(_ss, LOW);
spiwrite(W25Q16BV_CMD_PAGEPROG); // 0x02
spiwrite((address >> 16) & 0xFF); // address upper 8
spiwrite((address >> 8) & 0xFF); // address mid 8
if (len == 256)
{
// If len = 256 bytes, lower 8 bits must be 0 (see datasheet 11.2.17)
spiwrite(0);
}
else
{
spiwrite(address & 0xFF); // address lower 8
}
// Transfer data
for (i = 0; i < len; i++)
{
spiwrite(buffer[i]);
}
// Write only occurs after the CS line is de-asserted
digitalWrite(_ss, HIGH);
// Wait at least 3ms (max page program time according to datasheet)
delay(3);
// Wait until the device is ready or a timeout occurs
if (WaitForReady())
return 0;
return len;
}
