static void ide_itdm320_insw (unsigned long port, void *addr, u32 count)
{
volatile u16 *d_ptr;
unsigned long dest_addr;
if ( count <= SECTOR_WORDS ) {
readsw(port, addr, count);
return;
}
d_ptr = (volatile u16*) addr;
dest_addr = virt_to_phys((void*) d_ptr);
if (((u32) dest_addr) & 0x2) {
readsw(port, addr, 1);
dest_addr += 2;
count -= 2;
if (!count) return;
}//if
while (inw(IO_EMIF_DMACTL) & 0x0001); // wait for pending outsw() if any
outw(0x0830, IO_SDRAM_SDDMASEL); // MTC 1 burst DMA
outw(0x0003, IO_EMIF_DMAMTCSEL); // DMA MTC Select: CS3
outw(((port & 0x0FFF0000) >> 16) |
(1 << 15), IO_EMIF_MTCADDH);
outw(port & 0x0000FFFF, IO_EMIF_MTCADDL);
outw((dest_addr & 0x7FFF0000) >> 16, IO_EMIF_AHBADDH);
outw(dest_addr & 0x0000FFFF, IO_EMIF_AHBADDL);
SET_DMA_SIZE( count );
/* Start the DMA transfer */
outw(0x0002, IO_EMIF_DMACTL);
outw(inw(IO_EMIF_DMACTL) | 1, IO_EMIF_DMACTL);
// invalidate cache, so we read new data from DRAM
//arm926_dma_inv_range((unsigned long)addr, (unsigned long)addr + count );
consistent_sync( addr, count, DMA_FROM_DEVICE );
}
static void at91_ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
void *buf, unsigned int len)
{
ide_hwif_t *hwif = drive->hwif;
struct ide_io_ports *io_ports = &hwif->io_ports;
u8 chipselect = hwif->select_data;
unsigned long mode;
pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
len++;
enter_16bit(chipselect, mode);
readsw((void __iomem *)io_ports->data_addr, buf, len / 2);
leave_16bit(chipselect, mode);
}
static inline int oakscsi_pread(struct NCR5380_hostdata *hostdata,
unsigned char *addr, int len)
{
u8 __iomem *base = hostdata->io;
printk("reading %p len %d\n", addr, len);
while(len > 0)
{
unsigned int status, timeout;
unsigned long b;
timeout = 0x01FFFFFF;
while (((status = readw(base + STAT)) & 0x100)==0)
{
timeout--;
if(status & 0x200 || !timeout)
{
printk("status = %08X\n", status);
return -1;
}
}
if(len >= 128)
{
readsw(base + DATA, addr, 128);
addr += 128;
len -= 128;
}
else
{
b = (unsigned long) readw(base + DATA);
*addr ++ = b;
len -= 1;
if(len)
*addr ++ = b>>8;
len -= 1;
}
}
return 0;
}
static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *addr,
int len)
{
void __iomem *base = priv(instance)->base;
printk("reading %p len %d\n", addr, len);
while(len > 0)
{
unsigned int status, timeout;
unsigned long b;
timeout = 0x01FFFFFF;
while (((status = readw(base + STAT)) & 0x100)==0)
{
timeout--;
if(status & 0x200 || !timeout)
{
printk("status = %08X\n", status);
return 1;
}
}
if(len >= 128)
{
readsw(base + DATA, addr, 128);
addr += 128;
len -= 128;
}
else
{
b = (unsigned long) readw(base + DATA);
*addr ++ = b;
len -= 1;
if(len)
*addr ++ = b>>8;
len -= 1;
}
}
return 0;
}
static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
u16 *buf, int count)
{
readsw(host->ctl + (addr << host->bus_shift), buf, count);
}
static void ide_itdm320_insw (unsigned long port, void *addr, u32 count)
{
readsw(port, addr, count);
}
