/* * Set up the clock source and clock events devices */ void __init realview_timer_init(unsigned int timer_irq) { u32 val; /* * set clock frequency: * REALVIEW_REFCLK is 32KHz * REALVIEW_TIMCLK is 1MHz */ val = readl(__io_address(REALVIEW_SCTL_BASE)); writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, __io_address(REALVIEW_SCTL_BASE)); /* * Initialise to a known state (all timers off) */ writel(0, timer0_va_base + TIMER_CTRL); writel(0, timer1_va_base + TIMER_CTRL); writel(0, timer2_va_base + TIMER_CTRL); writel(0, timer3_va_base + TIMER_CTRL); /* * Make irqs happen for the system timer */ setup_irq(timer_irq, &realview_timer_irq); realview_clocksource_init(); realview_clockevents_init(timer_irq); }
/* * Set up the clock source and clock events devices */ void __init realview_timer_init(unsigned int timer_irq) { u32 val; #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST /* * The dummy clock device has to be registered before the main device * so that the latter will broadcast the clock events */ local_timer_setup(); #endif /* * set clock frequency: * REALVIEW_REFCLK is 32KHz * REALVIEW_TIMCLK is 1MHz */ val = readl(__io_address(REALVIEW_SCTL_BASE)); writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, __io_address(REALVIEW_SCTL_BASE)); /* * Initialise to a known state (all timers off) */ writel(0, timer0_va_base + TIMER_CTRL); writel(0, timer1_va_base + TIMER_CTRL); writel(0, timer2_va_base + TIMER_CTRL); writel(0, timer3_va_base + TIMER_CTRL); /* * Make irqs happen for the system timer */ setup_irq(timer_irq, &realview_timer_irq); realview_clocksource_init(); realview_clockevents_init(timer_irq); }