static int ioctl_get_opts(void *user_addr)
{
struct pme_ctrl_opts opts;
u32 val;
if (copy_from_user(&opts, user_addr, sizeof(opts)))
return -EFAULT;
if (opts.flags & PME_CTRL_OPT_SWDB)
opts.swdb = reg_get(regs, SWDB);
if (opts.flags & PME_CTRL_OPT_EOSRP) {
opts.eosrp = reg_get(regs, SREC);
opts.eosrp &= PME_DMA_EOSRP_MASK; /* 18 lower bits */
}
if (opts.flags & PME_CTRL_OPT_DRCC)
opts.drcc = reg_get(regs, DRCC);
if (opts.flags & PME_CTRL_OPT_KVLTS) {
val = reg_get(regs, KVLTS);
opts.kvlts = val + 1;
}
if (opts.flags & PME_CTRL_OPT_MCL) {
opts.mcl = reg_get(regs, KEC);
opts.mcl &= PME_DMA_MCL_MASK; /* 15 lower bits */
}
if (copy_to_user(user_addr, &opts, sizeof(opts)))
return -EFAULT;
return 0;
};
static int ioctl_set_opts(void *user_addr)
{
struct pme_ctrl_opts opts;
u32 val;
if (copy_from_user(&opts, user_addr, sizeof(opts)))
return -EFAULT;
/* Validation */
if (opts.flags & PME_CTRL_OPT_KVLTS)
if (opts.kvlts < 1 || opts.kvlts > 16)
return -EINVAL;
if (opts.flags & PME_CTRL_OPT_SWDB)
reg_set(regs, SWDB, opts.swdb);
if (opts.flags & PME_CTRL_OPT_EOSRP) {
val = reg_get(regs, SREC);
/* 18 lower bits */
val = (val & ~PME_DMA_EOSRP_MASK) |
(opts.eosrp & PME_DMA_EOSRP_MASK);
reg_set(regs, SREC, val);
}
if (opts.flags & PME_CTRL_OPT_DRCC)
reg_set(regs, DRCC, opts.drcc);
if (opts.flags & PME_CTRL_OPT_KVLTS) {
val = opts.kvlts - 1;
reg_set(regs, KVLTS, val);
}
if (opts.flags & PME_CTRL_OPT_MCL) {
val = reg_get(regs, KEC);
/* 15 lower bits */
val = (val & ~PME_DMA_MCL_MASK) |
(opts.mcl & PME_DMA_MCL_MASK);
reg_set(regs, KEC, val);
}
return 0;
};
static int ioctl_fbm(void *user_addr)
{
int loop;
u32 a, b;
struct pme_ctrl_fb fb;
fb.blocksize[0] = reg_get(regs, FBL0SIZE);
fb.blocksize[1] = reg_get(regs, FBL1SIZE);
fb.blocksize[2] = reg_get(regs, FBL2SIZE);
fb.blocksize[3] = reg_get(regs, FBL3SIZE);
fb.blocksize[4] = reg_get(regs, FBL4SIZE);
fb.blocksize[5] = reg_get(regs, FBL5SIZE);
fb.blocksize[6] = reg_get(regs, FBL6SIZE);
fb.blocksize[7] = reg_get(regs, FBL7SIZE);
a = reg_get(regs, FBLAAR);
b = reg_get(regs, FBLABR);
for (loop = (PME_CHANNEL_MAX - 1); loop >= 0; loop--) {
__fb_l_set(&fb.channels[loop].virt[0],
(a >> (8 * loop))&0xff);
__fb_l_set(&fb.channels[loop].virt[1],
(b >> (8 * loop))&0xff);
}
if (copy_to_user(user_addr, &fb, sizeof(fb)))
return -EFAULT;
return 0;
}
static int _init(netdev2_t *encdev)
{
encx24j600_t *dev = (encx24j600_t *) encdev;
DEBUG("encx24j600: starting initialization...\n");
/* setup IO */
gpio_init(dev->cs, GPIO_OUT);
gpio_set(dev->cs);
gpio_init_int(dev->int_pin, GPIO_IN_PU, GPIO_FALLING, encx24j600_isr, (void*)dev);
if (spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, ENCX24J600_SPI_SPEED) < 0) {
return -1;
}
lock(dev);
/* initialization procedure as described in data sheet (39935c.pdf) */
do {
do {
xtimer_usleep(ENCX24J600_INIT_DELAY);
reg_set(dev, ENC_EUDAST, 0x1234);
xtimer_usleep(ENCX24J600_INIT_DELAY);
} while (reg_get(dev, ENC_EUDAST) != 0x1234);
while (!(reg_get(dev, ENC_ESTAT) & ENC_CLKRDY));
/* issue System Reset */
cmd(dev, ENC_SETETHRST);
/* make sure initialization finalizes */
xtimer_usleep(1000);
} while (!(reg_get(dev, ENC_EUDAST) == 0x0000));
/* configure flow control */
phy_reg_set(dev, ENC_PHANA, 0x05E1);
reg_set_bits(dev, ENC_ECON2, ENC_AUTOFC);
/* setup receive buffer */
reg_set(dev, ENC_ERXST, RX_BUFFER_START);
reg_set(dev, ENC_ERXTAIL, RX_BUFFER_END);
dev->rx_next_ptr = RX_BUFFER_START;
/* configure receive filter to receive multicast frames */
reg_set_bits(dev, ENC_ERXFCON, ENC_MCEN);
/* setup interrupts */
reg_set_bits(dev, ENC_EIE, ENC_PKTIE | ENC_LINKIE);
cmd(dev, ENC_ENABLERX);
cmd(dev, ENC_SETEIE);
DEBUG("encx24j600: initialization complete.\n");
unlock(dev);
#ifdef MODULE_NETSTATS_L2
memset(&netdev->stats, 0, sizeof(netstats_t));
#endif
return 0;
}
static void _get_mac_addr(netdev2_t *encdev, uint8_t* buf)
{
encx24j600_t * dev = (encx24j600_t *) encdev;
uint16_t *addr = (uint16_t *) buf;
lock(dev);
addr[0] = reg_get(dev, MAADR1);
addr[1] = reg_get(dev, MAADR2);
addr[2] = reg_get(dev, MAADR3);
unlock(dev);
}
/* revision */
static int ioctl_rev(void *user_addr)
{
struct pme_ctrl_rev rev;
u32 rev1 = reg_get(regs, PME_IP_REV1);
u32 rev2 = reg_get(regs, PME_IP_REV2);
rev.ip_id = rev1 >> 16;
rev.ip_mj = (rev1 & 0x0000FF00) >> 8;
rev.ip_mn = rev1 & 0x000000FF;
rev.ip_int = (rev2 & 0x00FF0000) >> 16;
rev.ip_cfg = rev2 & 0x000000FF;
if (copy_to_user(user_addr, &rev, sizeof(rev)))
return -EFAULT;
return 0;
}
static void tn_dump_ep(tn_endpoint_t *fsep, int indent) {
const char *prefix = dump_indent(indent);
int newind = indent + 1;
const char *eppref = dump_indent(newind);
log_debug("%sprovider='%s';\n", prefix, fsep->base.ptype->name);
log_debug("%sis_temporary='%d';\n", prefix, fsep->base.is_temporary);
log_debug("%sis_assigned='%d';\n", prefix, fsep->base.is_assigned);
log_debug("%shostname='%d';\n", prefix, fsep->hostname);
log_debug("%sfiles={;\n", prefix);
for (int i = 0; ; i++) {
File *file = (File*) reg_get(&fsep->base.files, i);
log_debug("%s// file at %p\n", eppref, file);
if (file != NULL) {
log_debug("%s{\n", eppref, file);
if (file->file.handler->dump != NULL) {
file->file.handler->dump((file_t*)file, 0, newind+1);
}
log_debug("%s{\n", eppref, file);
} else {
break;
}
}
log_debug("%s}\n", prefix);
}
static int _send(netdev2_t *netdev, const struct iovec *vector, int count) {
encx24j600_t * dev = (encx24j600_t *) netdev;
lock(dev);
/* wait until previous packet has been sent */
while ((reg_get(dev, ECON1) & TXRTS));
/* copy packet to SRAM */
size_t len = 0;
for (int i = 0; i < count; i++) {
sram_op(dev, WGPDATA, (i ? 0xFFFF : TX_BUFFER_START), vector[i].iov_base, vector[i].iov_len);
len += vector[i].iov_len;
}
/* set start of TX packet and length */
reg_set(dev, ETXST, TX_BUFFER_START);
reg_set(dev, ETXLEN, len);
/* initiate sending */
cmd(dev, SETTXRTS);
/* wait for sending to complete */
/* (not sure if it is needed, keeping the line uncommented) */
/*while ((reg_get(dev, ECON1) & TXRTS));*/
unlock(dev);
return len;
}
static void _isr(netdev2_t *netdev)
{
encx24j600_t *dev = (encx24j600_t *) netdev;
uint16_t eir;
lock(dev);
cmd(dev, CLREIE);
eir = reg_get(dev, EIR);
/* check & handle link state change */
if (eir & LINKIF) {
uint16_t estat = reg_get(dev, ESTAT);
netdev2_event_t event = (estat & PHYLNK) ?
NETDEV2_EVENT_LINK_DOWN :
NETDEV2_EVENT_LINK_UP;
netdev->event_callback(netdev, event, NULL);
}
/* check & handle available packets */
if (eir & PKTIF) {
while (_packets_available(dev)) {
unlock(dev);
netdev->event_callback(netdev, NETDEV2_EVENT_RX_COMPLETE,
NULL);
lock(dev);
}
}
/* drop all flags */
reg_clear_bits(dev, EIR, LINKIF);
/* re-enable interrupt */
gpio_irq_enable(dev->int_pin);
cmd(dev, SETEIE);
unlock(dev);
}
/* This isr is invoked if an error occurs at the global level of the device
* There isn't much we can do other than log the occurance and disable the
* condition that caused the error */
static irqreturn_t global_isr(int irq, void *dev_id)
{
u32 status = reg_get(regs, ISRCC);
u32 enabled = reg_get(regs, IERCC);
if (!status)
/* The IRQ wasn't for us. Let the kernel try the next handler
* registered on this irq */
return IRQ_NONE;
printk(KERN_ERR PMMOD PME_CTRL_PATH
": Global Error ISR %d ISRCC is 0x%x\n", irq, status);
/* Disable these error bits from asserting the interrupt again */
reg_set(regs, IERCC, enabled & ~status);
/* We need to be sure the posted write to IERCC has taken affect before
* the ISR exits (otherwise it will refire unnecessarily). To this end,
* we read the register back and compare, ensuring the write has to
* complete first. NB, we don't need smp_mb() here or any such thing
* because the CPU can't reorder the initiation of the read/write pair
* due to the interdependency of the operations. */
if (reg_get(regs, IERCC) != (enabled & ~status))
printk(KERN_ERR PMMOD PME_CTRL_PATH ": IERCC inconsistency\n");
wake_up_all(&monitor_queue);
return IRQ_HANDLED;
}
static int ioctl_monitor(void *user_addr)
{
int res = 0;
struct pme_monitor_poll p;
if (copy_from_user(&p, user_addr, sizeof(p)))
return -EFAULT;
/* Disable bits as requested */
if (p.disable_mask)
reg_set(regs, ISDRCC, reg_get(regs, ISDRCC) | p.disable_mask);
/* Clear status bits corresponding to those requested as well as those
* disabled */
if (p.clear_mask | p.disable_mask)
reg_set(regs, ISRCC, p.clear_mask | p.disable_mask);
/* Re-enable bits we may have cleared in the enable register */
if (p.clear_mask)
reg_set(regs, IERCC, reg_get(regs, IERCC) | p.clear_mask);
if (p.block) {
if (p.timeout_ms) {
res = wait_event_interruptible_timeout(monitor_queue,
reg_get(regs, ISRCC) & ~(p.ignore_mask),
msecs_to_jiffies(p.timeout_ms));
if (res > 0)
res = 0;
else if (!res)
res = 1;
} else
res = wait_event_interruptible(monitor_queue,
reg_get(regs, ISRCC) & ~(p.ignore_mask));
if (res < 0)
res = -EINTR;
}
p.status = reg_get(regs, ISRCC);
if (copy_to_user(user_addr, &p, sizeof(p)))
return -EFAULT;
return res;
}
static void tnp_dump(int indent) {
const char *prefix = dump_indent(indent);
int newind = indent + 1;
const char *eppref = dump_indent(newind);
log_debug("%s// tcp system provider\n", prefix);
log_debug("%sendpoints={\n", prefix);
for (int i = 0; ; i++) {
tn_endpoint_t *fsep = (tn_endpoint_t*) reg_get(&endpoints, i);
if (fsep != NULL) {
log_debug("%s// endpoint %p\n", eppref, fsep);
log_debug("%s{\n", eppref);
tn_dump_ep(fsep, newind+1);
log_debug("%s}\n", eppref);
} else {
break;
}
}
log_debug("%s}\n", prefix);
}
static pic_value
reg_call(pic_state *pic)
{
struct pic_proc *self = pic_get_proc(pic);
struct pic_reg *reg;
pic_value key, val;
int n;
n = pic_get_args(pic, "o|o", &key, &val);
if (! pic_obj_p(key)) {
pic_errorf(pic, "attempted to set a non-object key '~s' in a register", key);
}
reg = pic_reg_ptr(pic_proc_env_ref(pic, self, "reg"));
if (n == 1) {
return reg_get(pic, reg, pic_obj_ptr(key));
} else {
return reg_set(pic, reg, pic_obj_ptr(key), val);
}
}
// reg_allocate - allocates a register to hold value
reg* reg_allocate(VALUE value){
reg *res, *reg;
reg=reg_get(); // reuse another register
// isVar(reg->value)
if(reg!=NULL && reg->dirty==true){
// saves 'reg' in memory (solution: check for other reg/ print the instruction?)
res=reg;
}
else
res=reg;
copy(res->value, value);
res->dist=-1;
res->free=false;
#ifdef VERBOSE
printf(" [reg_allocate]\t \'%s\' ~~~> \'%s\'\n", value, res->name);
#endif
return res;
}
void cpu_instr_cswap(const sInstrArgs *iargs) {
octa addr = iargs->y + iargs->z;
octa mem = mmu_readOcta(addr,MEM_SIDE_EFFECTS);
if(mem == reg_getSpecial(rP)) {
// we have the problem here that both reg_set and mmu_writeOcta might throw an exception
// therefore we use the following trick...
octa val = reg_get(iargs->x);
// first, set X to an arbitrary value. if it throws, we haven't change anything yet
reg_set(iargs->x,0);
// if not, we're here and reset the register
reg_set(iargs->x,val);
// if mmu_writeOcta throws, we haven't changed anything yet
mmu_writeOcta(addr,val,MEM_SIDE_EFFECTS);
// if not, we're here and set X again. but this can't throw again since it would have
// already done that before
reg_set(iargs->x,1);
}
else {
// reg_set has to be done first, because it might throw an exception
reg_set(iargs->x,0);
reg_setSpecial(rP,mem);
}
}
static int ioctl_sre_reset(void *user_addr)
{
struct pme_sre_reset reset_vals;
unsigned int i = 0, loop = 100000;
unsigned long reg_ptr = SRRV0;
if (copy_from_user(&reset_vals, user_addr, sizeof(reset_vals)))
return -EFAULT;
/* Validate ranges */
if ((reset_vals.rule_index > PME_DMA_SRE_INDEX_MAX) ||
(reset_vals.rule_increment > PME_DMA_SRE_INC_MAX) ||
(reset_vals.rule_repetitions > PME_DMA_SRE_REP_MAX) ||
(reset_vals.rule_reset_interval >
PME_DMA_SRE_INTERVAL_MAX))
return -ERANGE;
/* Check and make sure only one caller is present */
if (!atomic_dec_and_test(&sre_reset_lock)) {
/* Someone else is already in this call */
atomic_inc(&sre_reset_lock);
return -EBUSY;
};
/* All validated. Run the command */
for (; i < PME_SRE_RULE_VECTOR_SIZE; i++)
reg_set(regs, reg_ptr++, reset_vals.rule_vector[i]);
reg_set(regs, SRRFI, reset_vals.rule_index);
reg_set(regs, SRRI, reset_vals.rule_increment);
reg_set(regs, SRRWC, (0xFFF & reset_vals.rule_reset_interval) << 1 |
(reset_vals.rule_reset_priority ? 1 : 0));
/* Need to set SRRR last */
reg_set(regs, SRRR, reset_vals.rule_repetitions);
do {
mdelay(PME_DMA_SRE_POLL_MS);
} while (reg_get(regs, SRRR) || !(loop--));
atomic_inc(&sre_reset_lock);
return 0;
}
static bool bit_get(const addr_type address, const reg_type value) { return (static_cast<volatile reg_type>(reg_get(address) & static_cast<reg_type>(1UL << value)) != static_cast<reg_type>(0U)); }
static void reg_msk(const addr_type address, const reg_type value,
const reg_type mask_value) { *reinterpret_cast<volatile reg_type*>(address) = reg_type(reg_type(reg_get(address) & reg_type(~mask_value)) | reg_type(value & mask_value)); }
static void test_regunsave0(void) {
static octa specials[SPECIAL_NUM];
static octa locals[LREG_NUM];
static octa globals[GREG_NUM];
// set some state
reg_setSpecial(rG,100);
reg_setSpecial(rS,0x1000);
reg_setSpecial(rO,0x1000);
for(size_t i = 100; i < GREG_NUM; i++)
reg_setGlobal(i,i);
for(size_t i = 0; i < 10; i++)
reg_set(i,i);
// backup
for(size_t i = 0; i < LREG_NUM; i++)
locals[i] = reg_get(i);
for(size_t i = 100; i < GREG_NUM; i++)
globals[i] = reg_getGlobal(i);
for(size_t i = 0; i < SPECIAL_NUM; i++)
specials[i] = reg_getSpecial(i);
// arrange things so that an unsave fails at the beginning
{
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
for(size_t i = 0; i < LREG_NUM; i++)
test_assertOcta(reg_get(i),locals[i]);
for(size_t i = 100; i < GREG_NUM; i++)
test_assertOcta(reg_getGlobal(i),globals[i]);
for(size_t i = 0; i < SPECIAL_NUM; i++)
test_assertOcta(reg_getSpecial(i),specials[i]);
}
else {
ex_push(&env);
reg_unsave(STACK_ADDR,false);
test_assertFalse(true);
}
ex_pop();
}
// PTE 1 for 0x100000000 .. 0x1FFFFFFFF (---)
cache_write(CACHE_DATA,0x400000008,0x0000000400000000,0);
// PTE 2 for 0x200000000 .. 0x2FFFFFFFF (rwx)
cache_write(CACHE_DATA,0x400000010,0x0000000500000007,0);
// arrange things so that an unsave fails when reading rL
{
// set rG|rA
mmu_writeOcta(0x200000020,0xFE00000000000000,MEM_SIDE_EFFECTS);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
for(size_t i = 0; i < LREG_NUM; i++)
test_assertOcta(reg_get(i),locals[i]);
for(size_t i = 100; i < GREG_NUM; i++)
test_assertOcta(reg_getGlobal(i),globals[i]);
for(size_t i = 0; i < SPECIAL_NUM; i++)
test_assertOcta(reg_getSpecial(i),specials[i]);
}
else {
ex_push(&env);
reg_unsave(0x200000020,false);
test_assertFalse(true);
}
ex_pop();
}
// arrange things so that an unsave fails when testing the range
{
// set rG|rA
mmu_writeOcta(0x200000080,0xFE00000000000000,MEM_SIDE_EFFECTS);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
for(size_t i = 0; i < LREG_NUM; i++)
test_assertOcta(reg_get(i),locals[i]);
for(size_t i = 100; i < GREG_NUM; i++)
test_assertOcta(reg_getGlobal(i),globals[i]);
for(size_t i = 0; i < SPECIAL_NUM; i++)
test_assertOcta(reg_getSpecial(i),specials[i]);
}
else {
ex_push(&env);
reg_unsave(0x200000080,false);
test_assertFalse(true);
}
ex_pop();
}
// arrange things so that it works, but one value more would fail
{
// we have 13 specials, rL, rL locals and rG globals
octa off = (13 + 1 + 10 + (256 - 254) - 1) * sizeof(octa);
// set rG|rA
mmu_writeOcta(0x200000000 + off,0xFE00000000000000,MEM_SIDE_EFFECTS);
// rL is saved 13+rG positions further
mmu_writeOcta(0x200000000 + off - (13 + (256 - 254)) * sizeof(octa),10,MEM_SIDE_EFFECTS);
reg_unsave(0x200000000 + off,false);
test_assertTrue(true);
test_assertOcta(reg_getSpecial(rG),254);
test_assertOcta(reg_getSpecial(rL),10);
// this proves that one read more would have failed
test_assertOcta(reg_getSpecial(rS),0x200000000);
test_assertOcta(reg_getSpecial(rO),0x200000000);
}
// undo mapping
cache_write(CACHE_DATA,0x400000008,0,0);
cache_write(CACHE_DATA,0x400000010,0,0);
tc_removeAll(TC_DATA);
}
static int
get_error_msg (int err_code, char *msg_buf)
{
FILE *fp;
char *p;
int i;
char buf[1024];
char default_err_msg_file[PATH_MAX];
msg_buf[0] = '\0';
#ifdef DISPATCHER
strcpy (default_err_msg_file, ERROR_MSG_FILE);
#else
get_cubrid_file (FID_UV_ERR_MSG, default_err_msg_file);
#endif
#if defined(WINDOWS) && defined(DISPATCHER)
if (reg_get (REG_ERR_MSG, buf, sizeof (buf)) < 0)
return -1;
fp = fopen (buf, "r");
if (fp == NULL)
return -1;
#else
p = getenv ("UW_ER_MSG");
if (p == NULL)
{
fp = fopen (default_err_msg_file, "r");
}
else
{
fp = fopen (p, "r");
if (fp == NULL)
{
fp = fopen (default_err_msg_file, "r");
}
}
if (fp == NULL)
{
return -1;
}
#endif
for (i = 0; i < err_code; i++)
{
if (fgets (buf, sizeof (buf), fp) == NULL)
{
fclose (fp);
return -1;
}
}
if (fgets (buf, sizeof (buf), fp) == NULL)
{
fclose (fp);
return -1;
}
p = strchr (buf, ':');
if ((p == NULL) || (atoi (buf) != err_code))
{
fclose (fp);
return -1;
}
if (*(p + 1) == ' ')
p++;
strcpy (msg_buf, p + 1);
fclose (fp);
return 0;
}
/**
* returns the status of the execution
* 0 = normal end
* 1 = expect mismatch
*/
int execute_script(int sockfd, int toolsfd, registry_t *script) {
// current "pc" pointer to script line
int curpos = 0;
line_t *line = NULL;
int lineno = 0;
int err = 0;
ssize_t size = 0;
line_t *errmsg = NULL;
scriptlet_t *scr = NULL;
// guaranteed to be valid; toolsfd may be not set (<0)
int curfd = sockfd;
while ( (err == 0) && (line = reg_get(script, curpos)) != NULL) {
lineno = line->num;
switch (line->cmd) {
case CMD_COMMENT:
if (!trace) {
break;
}
// fall-through
case CMD_MESSAGE:
log_info("> %s\n", line->buffer);
break;
case CMD_ERRMSG:
errmsg = line;
break;
case CMD_SEND:
for (int i = 0; (scr = reg_get(&line->scriptlets, i)) != NULL; i++) {
if (scr->exec != NULL) {
scr->exec(line, scr);
}
}
if (trace) {
log_hexdump2(line->buffer, line->length, 0, "Send : ");
}
size = write(curfd, line->buffer, line->length);
if (size < 0) {
log_errno("Error writing to socket at line %d\n", lineno);
err = -1;
}
break;
case CMD_EXPECT:
line->mask = mem_alloc_c(line->length, "line_mask");
memset(line->mask, 0xff, line->length);
for (int i = 0; (scr = reg_get(&line->scriptlets, i)) != NULL; i++) {
if (scr->exec != NULL) {
scr->exec(line, scr);
}
}
err = compare_packet(curfd, line->buffer, line->mask, line->length, lineno);
mem_free(line->mask);
line->mask = NULL;
if (err != 0) {
if (errmsg != NULL) {
log_error("> %d: %s -> %d\n", lineno, errmsg->buffer, err);
}
return 1;
}
break;
case CMD_INIT:
send_sync(curfd);
err = compare_packet(curfd, line->buffer, NULL, line->length, lineno);
if (err != 0) {
if (errmsg != NULL) {
log_error("> %d: %s -> %d\n", lineno, errmsg->buffer, err);
}
return 1;
}
break;
case CMD_CHANNEL:
if ((!strcmp("tools", line->buffer)) && toolsfd >= 0) {
curfd = toolsfd;
} else
if ((!strcmp("device", line->buffer)) && sockfd >= 0) {
curfd = sockfd;
} else {
log_error("> %d: -> unknown channel name %s\n", lineno, line->buffer);
return 1;
}
break;
}
curpos++;
}
return 0;
}
static inline int _packets_available(encx24j600_t *dev)
{
/* return PKTCNT (low byte of ESTAT) */
return reg_get(dev, ESTAT) & ~0xFF00;
}
/**
* returns the status of the execution
* 0 = normal end
* 1 = expect mismatch
*/
int execute_script(int sockfd, registry_t *script) {
// current "pc" pointer to script line
int curpos = 0;
line_t *line = NULL;
int lineno = 0;
int err = 0;
ssize_t size = 0;
line_t *errmsg = NULL;
scriptlet_t *scr = NULL;
while ( (err == 0) && (line = reg_get(script, curpos)) != NULL) {
lineno = line->num;
switch (line->cmd) {
case CMD_COMMENT:
if (!trace) {
break;
}
// fall-through
case CMD_MESSAGE:
log_info("> %s\n", line->buffer);
break;
case CMD_ERRMSG:
errmsg = line;
break;
case CMD_SEND:
for (int i = 0; (scr = reg_get(&line->scriptlets, i)) != NULL; i++) {
if (scr->exec != NULL) {
scr->exec(line, scr);
}
}
if (trace) {
log_hexdump2(line->buffer, line->length, 0, "Send : ");
}
size = write(sockfd, line->buffer, line->length);
if (size < 0) {
log_errno("Error writing to socket at line %d\n", lineno);
err = -1;
}
break;
case CMD_EXPECT:
line->mask = mem_alloc_c(line->length, "line_mask");
memset(line->mask, 0xff, line->length);
for (int i = 0; (scr = reg_get(&line->scriptlets, i)) != NULL; i++) {
if (scr->exec != NULL) {
scr->exec(line, scr);
}
}
err = compare_packet(sockfd, line->buffer, line->mask, line->length, lineno);
mem_free(line->mask);
line->mask = NULL;
if (err != 0) {
if (errmsg != NULL) {
log_error("> %d: %s -> %d\n", lineno, errmsg->buffer, err);
}
return err;
}
break;
case CMD_INIT:
send_sync(sockfd);
err = compare_packet(sockfd, line->buffer, NULL, line->length, lineno);
if (err != 0) {
if (errmsg != NULL) {
log_error("> %d: %s -> %d\n", lineno, errmsg->buffer, err);
}
return err;
}
break;
}
curpos++;
}
return 0;
}
static void test_regset(void) {
reg_setSpecial(rG,255);
reg_setSpecial(rS,STACK_ADDR);
reg_setSpecial(rO,STACK_ADDR);
// first try, which does not change the state at all
{
reg_set(254,0x1234);
reg_push(254);
test_assertOcta(reg_get(0),0);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_get(0),0);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
}
else {
ex_push(&env);
reg_set(0,0x5678);
test_assertFalse(true);
}
ex_pop();
reg_pop(0);
}
// second try, which sets a few registers first
{
reg_setSpecial(rL,0);
reg_set(252,0x1234);
reg_push(252);
test_assertOcta(reg_get(0),0);
test_assertOcta(reg_get(1),0);
test_assertOcta(reg_get(2),0);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7E8);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_get(0),0);
test_assertOcta(reg_get(1),0);
test_assertOcta(reg_get(2),0);
test_assertOcta(reg_getSpecial(rL),2); // has changed
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7E8);
}
else {
ex_push(&env);
reg_set(2,0x5678);
test_assertFalse(true);
}
ex_pop();
reg_pop(0);
}
}
static sCmdArg eval_doFetchExp(int op,sASTNode *expr,octa offset,bool *finished) {
sCmdArg e = eval_get(expr,offset * fetchOps[op].width,finished);
if(e.type != ARGVAL_INT)
cmds_throwEx("Unsupported operation!\n");
sCmdArg res;
res.type = ARGVAL_INT;
res.origin = ORG_EXPR;
res.location = e.d.integer & ~(octa)(fetchOps[op].align - 1);
res.d.integer = 0;
// don't do anything when we're done because it may cause an error if we've crossed a "border"
// e.g. sp[31..32]. the last call would be for sp[33]
if(*finished)
return res;
switch(op) {
case FETCH_VMEM:
// be carefull with aligning here, therefore byte-access
res.d.integer = eval_vmReadOcta(res.location);
res.origin = ORG_VMEM;
break;
case FETCH_VMEM1:
// use the uncached version here because we don't want to change the machine-state (TC)
res.d.integer = mmu_readByte(res.location,0);
res.origin = ORG_VMEM1;
break;
case FETCH_VMEM2:
res.d.integer = mmu_readWyde(res.location,0);
res.origin = ORG_VMEM2;
break;
case FETCH_VMEM4:
res.d.integer = mmu_readTetra(res.location,0);
res.origin = ORG_VMEM4;
break;
case FETCH_VMEM8:
res.d.integer = mmu_readOcta(res.location,0);
res.origin = ORG_VMEM8;
break;
case FETCH_PMEM:
res.d.integer = bus_read(res.location,false);
res.origin = ORG_PMEM;
break;
case FETCH_LREG:
res.d.integer = reg_getLocal(res.location);
res.origin = ORG_LREG;
break;
case FETCH_GREG:
if(res.location < MAX(256 - GREG_NUM,MIN_GLOBAL))
cmds_throwEx("The global register %Od does not exist\n",res.location);
res.d.integer = reg_getGlobal(res.location);
res.origin = ORG_GREG;
break;
case FETCH_SREG:
if(res.location >= SPECIAL_NUM)
cmds_throwEx("The special register %Od does not exist\n",res.location);
res.d.integer = reg_getSpecial(res.location);
res.origin = ORG_SREG;
break;
case FETCH_DREG:
res.d.integer = reg_get(res.location);
res.origin = ORG_DREG;
break;
default:
assert(false);
break;
}
if(offset == 0)
*finished = false;
return res;
}
static void test_cswap(void) {
sInstrArgs iargs;
reg_setSpecial(rL,0);
reg_setSpecial(rG,255);
// arrange things so that reading the memory-location fails
{
// PTE 1 for 0x100000000 .. 0x1FFFFFFFF (-wx)
cache_write(CACHE_DATA,0x400000008,0x0000000400000003,0);
tc_removeAll(TC_DATA);
reg_setSpecial(rP,0x1234567890ABCDEF);
reg_set(10,0x1234);
mmu_writeOcta(0x100000000,0,MEM_SIDE_EFFECTS);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_getSpecial(rP),0x1234567890ABCDEF);
test_assertOcta(reg_get(10),0x1234);
test_assertOcta(cache_read(CACHE_DATA,0x400000000,MEM_SIDE_EFFECTS),0);
}
else {
ex_push(&env);
iargs.x = 10;
iargs.y = 0x100000000;
iargs.z = 0;
cpu_instr_cswap(&iargs);
test_assertFalse(true);
}
ex_pop();
}
// arrange things so that writing the memory-location fails
{
reg_setSpecial(rP,0x1234567890ABCDEF);
reg_set(10,0x1234);
mmu_writeOcta(0x100000000,0x1234567890ABCDEF,MEM_SIDE_EFFECTS);
// PTE 1 for 0x100000000 .. 0x1FFFFFFFF (r-x)
cache_write(CACHE_DATA,0x400000008,0x0000000400000005,0);
tc_removeAll(TC_DATA);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_getSpecial(rP),0x1234567890ABCDEF);
test_assertOcta(reg_get(10),0x1234);
test_assertOcta(mmu_readOcta(0x100000000,MEM_SIDE_EFFECTS),0x1234567890ABCDEF);
}
else {
ex_push(&env);
iargs.x = 10;
iargs.y = 0x100000000;
iargs.z = 0;
cpu_instr_cswap(&iargs);
test_assertFalse(true);
}
ex_pop();
}
// arrange things so that setting register X fails
{
// PTE 1 for 0x100000000 .. 0x1FFFFFFFF (rwx)
cache_write(CACHE_DATA,0x400000008,0x0000000400000007,0);
tc_removeAll(TC_DATA);
reg_setSpecial(rP,0x1234567890ABCDEF);
mmu_writeOcta(0x100000000,0x1234567890ABCDEF,MEM_SIDE_EFFECTS);
// push some registers down
reg_setSpecial(rO,STACK_ADDR);
reg_setSpecial(rS,STACK_ADDR);
reg_set(254,0x1234);
reg_push(254);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_getSpecial(rP),0x1234567890ABCDEF);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(mmu_readOcta(0x100000000,MEM_SIDE_EFFECTS),0x1234567890ABCDEF);
}
else {
ex_push(&env);
iargs.x = 10;
iargs.y = 0x100000000;
iargs.z = 0;
cpu_instr_cswap(&iargs);
test_assertFalse(true);
}
ex_pop();
}
}
/* Read global stats */
static int ioctl_stats(void *user_addr)
{
struct pme_ctrl_stats stats;
if (copy_from_user(&stats, user_addr, sizeof(stats)))
return -EFAULT;
if (stats.flags & PME_CTRL_STNIB)
stats.stnib = reg_get(regs, STNIB);
if (stats.flags & PME_CTRL_STNIS)
stats.stnis = reg_get(regs, STNIS);
if (stats.flags & PME_CTRL_STNTH1)
stats.stnth1 = reg_get(regs, STNTH1);
if (stats.flags & PME_CTRL_STNTH2)
stats.stnth2 = reg_get(regs, STNTH2);
if (stats.flags & PME_CTRL_STNTHL)
stats.stnthl = reg_get(regs, STNTHL);
if (stats.flags & PME_CTRL_STNCH)
stats.stnch = reg_get(regs, STNCH);
if (stats.flags & PME_CTRL_STNPM)
stats.stnpm = reg_get(regs, STNPM);
if (stats.flags & PME_CTRL_STNS1M)
stats.stns1m = reg_get(regs, STNS1M);
if (stats.flags & PME_CTRL_STNPMR)
stats.stnpmr = reg_get(regs, STNPMR);
if (stats.flags & PME_CTRL_STNDSR)
stats.stndsr = reg_get(regs, STNDSR);
if (stats.flags & PME_CTRL_STNESR)
stats.stnesr = reg_get(regs, STNESR);
if (stats.flags & PME_CTRL_STNS1R)
stats.stns1r = reg_get(regs, STNS1R);
if (stats.flags & PME_CTRL_STNOB)
stats.stnob = reg_get(regs, STNOB);
if (stats.flags & PME_CTRL_STDBC)
stats.stdbc = reg_get(regs, STDBC);
if (stats.flags & PME_CTRL_STDBP)
stats.stdbp = reg_get(regs, STDBP);
if (stats.flags & PME_CTRL_STDWC)
stats.stdwc = reg_get(regs, STDWC);
if (stats.flags & PME_CTRL_MIA_BYC)
stats.mia_byc = reg_get(regs, MIA_BYC);
if (stats.flags & PME_CTRL_MIA_BLC)
stats.mia_blc = reg_get(regs, MIA_BLC);
if (stats.flags & PME_CTRL_MIA_LSHC0)
stats.mia_lshc0 = reg_get(regs, MIA_LSHC0);
if (stats.flags & PME_CTRL_MIA_LSHC1)
stats.mia_lshc1 = reg_get(regs, MIA_LSHC1);
if (stats.flags & PME_CTRL_MIA_LSHC2)
stats.mia_lshc2 = reg_get(regs, MIA_LSHC2);
if (stats.flags & PME_CTRL_MIA_CWC0)
stats.mia_cwc0 = reg_get(regs, MIA_CWC0);
if (stats.flags & PME_CTRL_MIA_CWC1)
stats.mia_cwc1 = reg_get(regs, MIA_CWC1);
if (stats.flags & PME_CTRL_MIA_CWC2)
stats.mia_cwc2 = reg_get(regs, MIA_CWC2);
if (stats.flags & PME_CTRL_STNTHS)
stats.stnths = reg_get(regs, STNTHS);
stats.overflow = reg_get(regs, SCOS) & stats.flags;
/* Write-to-clear the overflow bits. Those stats that have been read
* have already been reset so it's necessary to do likewise with the
* overflow bits. NB, we have sleep interfaces available to allow an
* application to check the stats "often", however there's always a
* theoretical possibility for wrap-arounds to occur and thus give us
* "race" potentials between the stats and their overflow bits (there
* is no way to read them together atomically. We read/reset overflow
* bits after the stats to give us the least-worst combination. */
reg_set(regs, SCOS, stats.overflow);
if (copy_to_user(user_addr, &stats, sizeof(stats)))
return -EFAULT;
return 0;
}
