void tz_set_module_apc(unsigned int module, E_MASK_DOM domain_num , APC_ATTR permission_control)
{
volatile unsigned int* base = 0;
unsigned int clr_bit = 0x3 << ((module % MOD_NO_IN_1_DEVAPC) * 2);
unsigned int set_bit = permission_control << ((module % MOD_NO_IN_1_DEVAPC) * 2);
if(domain_num == E_DOMAIN_0)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D0_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_1)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D1_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_2)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D2_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_3)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D3_APC_0 + (module/16) *4);
}
#ifdef DBG_PRELOADER
MSG(DOM, "(B)tz_set_module_apc is (0x%x) 0x%x\n", base, reg_read32(base));
#endif
reg_write32(base, reg_read32(base) & ~clr_bit);
reg_write32(base, reg_read32(base) | set_bit);
#ifdef DBG_PRELOADER
MSG(DOM, "(E)tz_set_module_apc is (0x%x) 0x%x\n", base, reg_read32(base));
#endif
}
int32
cx23882_int(void *data)
{
cx23882_device *device = data;
uint32 mstat;
uint32 wmstat;
mstat = reg_read32(REG_PCI_INT_MSTAT);
if (!mstat)
return B_UNHANDLED_INTERRUPT;
if (mstat & (PCI_INT_STAT_HST_INT | PCI_INT_STAT_VIP_INT | PCI_INT_STAT_AUD_INT | PCI_INT_STAT_VID_INT)) {
// serious error, these bits should not be set
dprintf("cx23882_int error: msk 0x%08" B_PRIx32 ", stat 0x%08" B_PRIx32
", mstat 0x%08" B_PRIx32 "\n", reg_read32(REG_PCI_INT_MSK),
reg_read32(REG_PCI_INT_STAT), mstat);
reg_write32(REG_PCI_INT_MSK, 0);
return B_HANDLED_INTERRUPT;
}
wmstat = mstat & ~(PCI_INT_STAT_HST_INT | PCI_INT_STAT_VIP_INT | PCI_INT_STAT_TS_INT | PCI_INT_STAT_AUD_INT | PCI_INT_STAT_VID_INT);
if (wmstat)
reg_write32(REG_PCI_INT_STAT, wmstat);
if (wmstat)
dprintf("cx23882_int got 0x%08" B_PRIx32 "\n", wmstat);
if (mstat & PCI_INT_STAT_TS_INT) {
cx23882_mpegts_int(device);
return B_INVOKE_SCHEDULER;
} else {
return B_HANDLED_INTERRUPT;
}
}
void device_APC_dom_setup(void)
{
MSG(DOM, "\nDevice APC domain init setup:\n\n");
reg_write32(DEVAPC0_APC_CON, 0x0);
#ifdef DBG_PRELOADER
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_APC_CON));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
#if defined(MACH_TYPE_MT6735)
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONN2AP, DOMAIN_2);
/*Set modem1 master to DOMAIN5*/
reg_set_field(DEVAPC0_MAS_DOM_2 , MD3_DOMAIN, DOMAIN_5);
/*Set gpu master to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_2 , GPU, DOMAIN_6);
#elif defined(MACH_TYPE_MT6735M)
// Notice: Compare to Denali-2: (1)Denali-2 does not have Master "MD3" (2)Denali-2 does not have Domain 4, 5, 6, 7.
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_0 , CONN2AP, DOMAIN_2);
/*Set gpu master to DOMAIN3*/
reg_set_field(DEVAPC0_MAS_DOM_1 , GPU, DOMAIN_3);
#elif defined(MACH_TYPE_MT6753)
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONN2AP, DOMAIN_2);
/*Set modem1 master to DOMAIN5*/
reg_set_field(DEVAPC0_MAS_DOM_2 , MD3_DOMAIN, DOMAIN_5);
/*Set gpu master to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_2 , GPU, DOMAIN_6);
#else
#error "Wrong MACH type"
#endif
#ifdef DBG_PRELOADER
MSG(DOM, "Device APC domain after setup:\n");
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
}
status_t
cx23882_stop_capture(cx23882_device *device)
{
TRACE("cx23882_stop_capture\n");
// stop RISC processor and DMA
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) & ~(TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN));
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) & ~DEV_CNTRL2_RUN_RISC);
return B_OK;
}
void tz_dapc_sec_init()
{
#ifdef DBG_PRELOADER
MSG(DOM, "(B)tz_dapc_sec_init is 0x%x\n", reg_read32(DEVAPC0_APC_CON));
#endif
reg_set_field(DEVAPC0_APC_CON , DEVAPC_APC_CON_CTRL, DEVAPC_APC_CON_EN);
tz_dapc_set_master_transaction(MASTER_MSDC0 , SECURE_TRAN);
#ifdef DBG_PRELOADER
MSG(DOM, "(E)tz_dapc_sec_init is 0x%x\n", reg_read32(DEVAPC0_APC_CON));
#endif
}
status_t
cx23882_init(cx23882_device *device)
{
// assumes that cx23882_reset() has already been called
status_t err;
if ((err = cx23882_buffers_alloc(device)) < B_OK) {
dprintf("cx23882: Error, buffer alloc failed\n");
return err;
}
device->capture_size = DMA_BUFFER_SIZE;
cx23882_via_sis_fixup(device);
// Set FIFO thresholds, should be 0 < x <= 7
reg_write32(REG_PDMA_STHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
reg_write32(REG_PDMA_DTHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
// init risc programm
cx23882_risc_ram_setup(device);
// init sram
cx23882_sram_setup(device);
// Reset counter to 0
reg_write32(REG_TS_GP_CNT_CNTRL, 0x3);
// Line length for RISC DMA
reg_write32(REG_TS_LNGTH, BYTES_PER_LINE);
// Set serial interface mode
reg_write32(REG_TS_GEN_CONTROL, reg_read32(REG_TS_GEN_CONTROL) | TS_GEN_CONTROL_IPB_SMODE);
// Setup hardware MPEG2 fec interface
reg_write32(REG_HW_SOP_CONTROL, (MPEG2_SYNC_BYTE << 16) | (MPEG2_PACKET_SIZE << 4) | SYNC_PACKET_COUNT);
// Setup TSSTOP status, active low, rising and falling edge, single bit width
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) | 0x18000);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) & ~0x06000);
// Enable interrupts for MPEG TS and all errors
reg_write32(REG_PCI_INT_MSK, reg_read32(REG_PCI_INT_MSK) | PCI_INT_STAT_TS_INT | 0x00fc00);
reg_write32(REG_TS_INT_MSK, reg_read32(REG_TS_INT_MSK) | TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2 | 0x1f1100);
TRACE("cx23882_init done\n");
return B_OK;
}
static uint32_t tnetw1130_read1l(tnetw1130_t *s, hwaddr addr)
{
assert(addr < TNETW1130_MEM1_SIZE);
uint32_t value = reg_read32(s->mem1, addr);
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname1(addr), value));
return value;
}
static uint32_t tnetw1130_read0l(tnetw1130_t *s, hwaddr addr)
{
uint32_t value = 0;
assert(addr < TNETW1130_MEM0_SIZE);
value = reg_read32(s->mem0, addr);
if (0) {
} else if (addr == TNETW1130_SLV_MEM_DATA) {
value = reg_read32(s->fw, s->fw_addr);
} else if (addr == TNETW1130_CMD_MAILBOX_OFFS) {
value = CMD_MAILBOX;
} else if (addr == TNETW1130_INFO_MAILBOX_OFFS) {
value = INFO_MAILBOX;
}
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname(addr), value));
return value;
}
int gpio_AckoutFreqSel(unsigned long Freq)
{
unsigned long tmpRead = 0;
unsigned long tmpClkV = -1;
switch(Freq) {
case 54:
tmpClkV = 0x0;
break;
case 27:
tmpClkV = 0x1;
break;
case 24:
tmpClkV = 0x2;
break;
default:
tmpClkV = -1;
break;
}
if(-1 != tmpClkV) {
tmpRead = reg_read32(PERI_CRG_REG(11));
tmpRead &= 0xFFF3FFFF;
tmpRead |= (tmpClkV << 18);
reg_write32(PERI_CRG_REG(11), tmpRead);
reg_write32(IO_CONFIG_REG(0), 1); //VI_ADC_CLK
return 0;
}
return -1;
}
static uint32_t tnetw1130_read1l(pci_tnetw1130_t * d, target_phys_addr_t addr)
{
tnetw1130_t *s = &d->tnetw1130;
assert(addr < TNETW1130_MEM1_SIZE);
uint32_t value = reg_read32(s->mem1, addr);
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname1(addr), value));
return value;
}
void device_APC_dom_setup(void)
{
MSG(DOM, "\nDevice APC domain init setup:\n\n");
reg_write32(DEVAPC0_APC_CON, 0x0);
#ifdef DBG_PRELOADER
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
/*Set modem master to DOMAIN1(MD0),DOMAIN5(MD1)*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD1_AHB_0, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_AXI_1, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_AXI_2, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AHB_0, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AXI_1, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AXI_2, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONNSYS, DOMAIN_2);
/*Set MD32 to DOMAIN3*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD32 , DOMAIN_3);
/*Set MFG to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MFG , DOMAIN_6);
#ifdef DBG_PRELOADER
MSG(DOM, "Device APC domain after setup:\n");
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
}
static void
cx23882_via_sis_fixup(cx23882_device *device)
{
uint16 host_vendor;
uint32 dev_cntrl1;
host_vendor = gPci->read_pci_config(0, 0, 0, PCI_vendor_id, 2);
dev_cntrl1 = reg_read32(REG_F2_DEV_CNTRL1);
if (host_vendor == PCI_VENDOR_VIA || host_vendor == PCI_VENDOR_SIS) {
dprintf("cx23882: enabling VIA/SIS compatibility mode\n");
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 | F2_DEV_CNTRL1_EN_VSFX);
} else {
dprintf("cx23882: disabling VIA/SIS compatibility mode\n");
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 & ~F2_DEV_CNTRL1_EN_VSFX);
}
}
static inline void
cx23882_mpegts_int(cx23882_device *device)
{
uint32 mstat = reg_read32(REG_TS_INT_MSTAT);
reg_write32(REG_TS_INT_STAT, mstat);
// dprintf("cx23882_mpegts_int got 0x%08lx\n", mstat);
if (mstat & TS_INT_STAT_OPC_ERR) {
dprintf("cx23882_mpegts_int RISC opcode error\n");
reg_write32(REG_PCI_INT_MSK, 0);
return;
}
if ((mstat & (TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2)) == (TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2)) {
dprintf("cx23882_mpegts_int both buffers ready\n");
mstat = TS_INT_STAT_TS_RISC1;
}
if (mstat & TS_INT_STAT_TS_RISC1) {
int32 count;
// dprintf("cx23882_mpegts_int buffer 1 at %Ld\n", system_time());
device->capture_data = device->dma_buf1_virt;
device->capture_end_time = system_time();
get_sem_count(device->capture_sem, &count);
if (count <= 0)
release_sem_etc(device->capture_sem, 1, B_DO_NOT_RESCHEDULE);
}
if (mstat & TS_INT_STAT_TS_RISC2) {
int32 count;
// dprintf("cx23882_mpegts_int buffer 2 at %Ld\n", system_time());
device->capture_data = device->dma_buf2_virt;
device->capture_end_time = system_time();
get_sem_count(device->capture_sem, &count);
if (count <= 0)
release_sem_etc(device->capture_sem, 1, B_DO_NOT_RESCHEDULE);
}
}
