void baytrail_init_scc(void)
{
uint32_t dll_values;
printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
/* Common Sideband Initialization for SCC */
reg_script_run(scc_start_dll);
/* Override Slave Path - populate DLL settings. */
dll_values = iosf_score_read(0x496c) & 0x7ffff;
dll_values |= iosf_score_read(0x4950) & ~0xfffff;
iosf_score_write(0x4950, dll_values | (1 << 19));
reg_script_run(scc_after_dll);
}
static void usb2_phy_init(device_t dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700),
/* Per port phy settings, set in devicetree.cb */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
config->usb2_per_port_lane0),
REG_IOSF_WRITE(IOSF_PORT_USBPHY,
USBPHY_PER_PORT_RCOMP_HS_PULLUP0,
config->usb2_per_port_rcomp_hs_pullup0),
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1,
config->usb2_per_port_lane1),
REG_IOSF_WRITE(IOSF_PORT_USBPHY,
USBPHY_PER_PORT_RCOMP_HS_PULLUP1,
config->usb2_per_port_rcomp_hs_pullup1),
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2,
config->usb2_per_port_lane2),
REG_IOSF_WRITE(IOSF_PORT_USBPHY,
USBPHY_PER_PORT_RCOMP_HS_PULLUP2,
config->usb2_per_port_rcomp_hs_pullup2),
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3,
config->usb2_per_port_lane3),
REG_IOSF_WRITE(IOSF_PORT_USBPHY,
USBPHY_PER_PORT_RCOMP_HS_PULLUP3,
config->usb2_per_port_rcomp_hs_pullup3),
REG_SCRIPT_END
};
reg_script_run(usb2_phy_script);
}
void pcie_init(void)
{
/* Initialize the PCIe bridges */
reg_script_run(pcie_init_script);
reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script);
reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script);
}
void car_mainboard_pre_console_init(void)
{
const struct reg_script *script;
/* Initialize the GPIO controllers */
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_gpio_init;
else
script = gen1_gpio_init;
reg_script_run(script);
/* Initialize the RXD and TXD paths for UART0 */
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_hsuart0;
else
script = (reg_legacy_gpio_read(
R_QNC_GPIO_RGLVL_RESUME_WELL)
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
? gen1_hsuart0_0x20 : gen1_hsuart0_0x21;
reg_script_run(script);
}
}
static void xhci_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
if (config && config->usb_comp_bg) {
struct reg_script ops[] = {
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
config->usb_comp_bg),
REG_SCRIPT_END
};
printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n",
config->usb_comp_bg);
reg_script_run(ops);
}
}
static void baytrail_core_init(device_t cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
/* On bay trail the turbo disable bit is actually scoped at building
* block level -- not package. For non-bsp cores that are within a
* building block enable turbo. The cores within the BSP's building
* block will just see it already enabled and move on. */
if (lapicid())
enable_turbo();
/* Set core MSRs */
reg_script_run(core_msr_script);
/* Set this core to max frequency ratio */
set_max_freq();
}
void mainboard_gpio_i2c_init(device_t dev)
{
const struct reg_script *script;
printk(BIOS_INFO, "Galileo I2C chip initialization\n");
/* Determine the correct script for the board */
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_i2c_init;
else
/* Determine which I2C address is in use */
script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
/* Initialize the I2C chips */
reg_script_run(script);
}
void soc_init_cpus(device_t dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
struct mp_params mp_params;
void *default_smm_area;
uint32_t bsmrwac;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
/* Set up MTRRs based on physical address size. */
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(pattrs->address_bits, 2);
x86_mtrr_check();
mp_params.num_cpus = pattrs->num_cpus,
mp_params.parallel_microcode_load = 1,
mp_params.adjust_apic_id = adjust_apic_id;
mp_params.flight_plan = &mp_steps[0];
mp_params.num_records = ARRAY_SIZE(mp_steps);
mp_params.microcode_pointer = pattrs->microcode_patch;
default_smm_area = backup_default_smm_area();
/*
* Configure the BUNIT to allow dirty cache line evictions in non-SMM
* mode for the lines that were dirtied while in SMM mode. Otherwise
* the writes would be silently dropped.
*/
bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
/* Set package MSRs */
reg_script_run(package_msr_script);
/* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
enable_turbo();
if (mp_init(cpu_bus, &mp_params))
printk(BIOS_ERR, "MP initialization failure.\n");
restore_default_smm_area(default_smm_area);
}
static void chip_init(void *chip_info)
{
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
/* Set the temperature settings */
reg_script_run(thermal_init_script);
/* Verify that the thermal configuration is locked */
ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
& (TS_LOCK_THRM_CTRL_REGS_ENABLE
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
== (TS_LOCK_THRM_CTRL_REGS_ENABLE
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
fsp_silicon_init();
}
void bootblock_soc_early_init(void)
{
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY))
light_sd_led();
/* Initialize the MTRRs */
reg_script_run(mtrr_init);
/* Initialize the controllers */
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
/* Enable the HSUART */
if (CONFIG(ENABLE_BUILTIN_HSUART0))
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
if (CONFIG(ENABLE_BUILTIN_HSUART1))
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT))
light_sd_led();
}
static void soc_core_init(device_t cpu)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(cpu));
printk(BIOS_DEBUG, "Init Braswell core.\n");
/*
* The turbo disable bit is actually scoped at building
* block level -- not package. For non-bsp cores that are within a
* building block enable turbo. The cores within the BSP's building
* block will just see it already enabled and move on.
*/
if (lapicid())
enable_turbo();
/* Set core MSRs */
reg_script_run(core_msr_script);
/* Set this core to max frequency ratio */
set_max_freq();
}
static void pre_mp_init(void)
{
uint32_t bsmrwac;
/* Set up MTRRs based on physical address size. */
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
/*
* Configure the BUNIT to allow dirty cache line evictions in non-SMM
* mode for the lines that were dirtied while in SMM mode. Otherwise
* the writes would be silently dropped.
*/
bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
/* Set package MSRs */
reg_script_run(package_msr_script);
/* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
enable_turbo();
}
static void dptf_init(void *unused)
{
printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n");
reg_script_run(dptf_init_settings);
}
static void perf_power(void *unused)
{
printk(BIOS_DEBUG, "Applying perf/power settings.\n");
reg_script_run(perf_power_settings);
}
