int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; SI val; check_desc (sd); if (!check_regno (regno)) return -1; size = reg_size (regno); if (length != size) return -1; val = get_le (buf, length); if (regno == sim_rl78_pc_regnum) { pc = val; /* The rl78 program counter is 20 bits wide. Ensure that GDB hasn't picked up any stray bits. This has occurred when performing a GDB "return" command in which the return address is obtained from a 32-bit container on the stack. */ assert ((pc & ~0x0fffff) == 0); } else memory[reg_addr (regno)] = val; return size; }
int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; SI val; check_desc (sd); if (!check_regno (regno)) return 0; size = reg_size (regno); if (length != size) return 0; if (regno == sim_rl78_pc_regnum) val = pc; else val = memory[reg_addr (regno)]; put_le (buf, length, val); return size; }
// free the endpoint descriptor static void tnp_do_free(endpoint_t *ep) { tn_endpoint_t *cep = (tn_endpoint_t*) ep; if (reg_size(&ep->files)) { log_warn("tcp_free(): trying to close endpoint %p with %d open files!\n", ep, reg_size(&ep->files)); return; } if (ep->is_assigned > 0) { log_warn("tcp_free(): trying to free endpoint %p still assigned\n", ep); return; } reg_remove(&endpoints, cep); mem_free(cep->hostname); mem_free(ep); }
Problem::Problem (Input input_param) { /* Retrieve input parameters */ int num_reg = input_param.get_num_reg(); Col<int> num_cells = input_param.get_num_cells(); vec reg_size = input_param.get_reg_size(); string quad_type = input_param.get_quad_type(); Col<int> quad_order = input_param.get_quad_order(); vec abs_xs = input_param.get_abs_xs(); vec scat_xs = input_param.get_scat_xs(); vec ext_source = input_param.get_ext_source(); /* Create vector of pointers to each region */ Regions.resize(num_reg); for (int i=0; i<num_reg; i++){ Regions[i] = new Region(quad_order(i), num_cells(i), reg_size(i), \ abs_xs(i), scat_xs(i), ext_source(i), quad_type); } }
int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; SI val; check_desc (sd); if (!check_regno (regno)) return -1; size = reg_size (regno); if (length != size) return -1; val = get_le (buf, length); if (regno == sim_rl78_pc_regnum) pc = val; else memory[reg_addr (regno)] = val; return size; }
int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; check_desc (sd); if (!check_regno (regno)) return -1; size = reg_size (regno); if (length == size) { DI val = get_le (buf, length); switch (regno) { case m32c_sim_reg_r0_bank0: regs.r[0].r_r0 = val & 0xffff; break; case m32c_sim_reg_r1_bank0: regs.r[0].r_r1 = val & 0xffff; break; case m32c_sim_reg_r2_bank0: regs.r[0].r_r2 = val & 0xffff; break; case m32c_sim_reg_r3_bank0: regs.r[0].r_r3 = val & 0xffff; break; case m32c_sim_reg_a0_bank0: regs.r[0].r_a0 = val & addr_mask; break; case m32c_sim_reg_a1_bank0: regs.r[0].r_a1 = val & addr_mask; break; case m32c_sim_reg_fb_bank0: regs.r[0].r_fb = val & addr_mask; break; case m32c_sim_reg_sb_bank0: regs.r[0].r_sb = val & addr_mask; break; case m32c_sim_reg_r0_bank1: regs.r[1].r_r0 = val & 0xffff; break; case m32c_sim_reg_r1_bank1: regs.r[1].r_r1 = val & 0xffff; break; case m32c_sim_reg_r2_bank1: regs.r[1].r_r2 = val & 0xffff; break; case m32c_sim_reg_r3_bank1: regs.r[1].r_r3 = val & 0xffff; break; case m32c_sim_reg_a0_bank1: regs.r[1].r_a0 = val & addr_mask; break; case m32c_sim_reg_a1_bank1: regs.r[1].r_a1 = val & addr_mask; break; case m32c_sim_reg_fb_bank1: regs.r[1].r_fb = val & addr_mask; break; case m32c_sim_reg_sb_bank1: regs.r[1].r_sb = val & addr_mask; break; case m32c_sim_reg_usp: regs.r_usp = val & addr_mask; break; case m32c_sim_reg_isp: regs.r_isp = val & addr_mask; break; case m32c_sim_reg_pc: regs.r_pc = val & membus_mask; break; case m32c_sim_reg_intb: regs.r_intbl = (val & membus_mask) & 0xffff; regs.r_intbh = (val & membus_mask) >> 16; break; case m32c_sim_reg_flg: regs.r_flags = val & 0xffff; break; /* These registers aren't implemented by the minisim. */ case m32c_sim_reg_svf: case m32c_sim_reg_svp: case m32c_sim_reg_vct: case m32c_sim_reg_dmd0: case m32c_sim_reg_dmd1: case m32c_sim_reg_dct0: case m32c_sim_reg_dct1: case m32c_sim_reg_drc0: case m32c_sim_reg_drc1: case m32c_sim_reg_dma0: case m32c_sim_reg_dma1: case m32c_sim_reg_dsa0: case m32c_sim_reg_dsa1: case m32c_sim_reg_dra0: case m32c_sim_reg_dra1: return 0; default: fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", regno); return 0; } }
int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; check_desc (sd); if (!check_regno (regno)) return 0; size = reg_size (regno); if (length == size) { DI val; switch (regno) { case m32c_sim_reg_r0_bank0: val = regs.r[0].r_r0; break; case m32c_sim_reg_r1_bank0: val = regs.r[0].r_r1; break; case m32c_sim_reg_r2_bank0: val = regs.r[0].r_r2; break; case m32c_sim_reg_r3_bank0: val = regs.r[0].r_r3; break; case m32c_sim_reg_a0_bank0: val = regs.r[0].r_a0; break; case m32c_sim_reg_a1_bank0: val = regs.r[0].r_a1; break; case m32c_sim_reg_fb_bank0: val = regs.r[0].r_fb; break; case m32c_sim_reg_sb_bank0: val = regs.r[0].r_sb; break; case m32c_sim_reg_r0_bank1: val = regs.r[1].r_r0; break; case m32c_sim_reg_r1_bank1: val = regs.r[1].r_r1; break; case m32c_sim_reg_r2_bank1: val = regs.r[1].r_r2; break; case m32c_sim_reg_r3_bank1: val = regs.r[1].r_r3; break; case m32c_sim_reg_a0_bank1: val = regs.r[1].r_a0; break; case m32c_sim_reg_a1_bank1: val = regs.r[1].r_a1; break; case m32c_sim_reg_fb_bank1: val = regs.r[1].r_fb; break; case m32c_sim_reg_sb_bank1: val = regs.r[1].r_sb; break; case m32c_sim_reg_usp: val = regs.r_usp; break; case m32c_sim_reg_isp: val = regs.r_isp; break; case m32c_sim_reg_pc: val = regs.r_pc; break; case m32c_sim_reg_intb: val = regs.r_intbl * 65536 + regs.r_intbl; break; case m32c_sim_reg_flg: val = regs.r_flags; break; /* These registers aren't implemented by the minisim. */ case m32c_sim_reg_svf: case m32c_sim_reg_svp: case m32c_sim_reg_vct: case m32c_sim_reg_dmd0: case m32c_sim_reg_dmd1: case m32c_sim_reg_dct0: case m32c_sim_reg_dct1: case m32c_sim_reg_drc0: case m32c_sim_reg_drc1: case m32c_sim_reg_dma0: case m32c_sim_reg_dma1: case m32c_sim_reg_dsa0: case m32c_sim_reg_dsa1: case m32c_sim_reg_dra0: case m32c_sim_reg_dra1: return 0; default: fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", regno); return -1; } put_le (buf, length, val); } return size; }
int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; DI val; check_desc (sd); if (!check_regno (regno)) return 0; size = reg_size (regno); if (length != size) return 0; if (rx_big_endian) val = get_be (buf, length); else val = get_le (buf, length); switch (regno) { case sim_rx_r0_regnum: put_reg (0, val); break; case sim_rx_r1_regnum: put_reg (1, val); break; case sim_rx_r2_regnum: put_reg (2, val); break; case sim_rx_r3_regnum: put_reg (3, val); break; case sim_rx_r4_regnum: put_reg (4, val); break; case sim_rx_r5_regnum: put_reg (5, val); break; case sim_rx_r6_regnum: put_reg (6, val); break; case sim_rx_r7_regnum: put_reg (7, val); break; case sim_rx_r8_regnum: put_reg (8, val); break; case sim_rx_r9_regnum: put_reg (9, val); break; case sim_rx_r10_regnum: put_reg (10, val); break; case sim_rx_r11_regnum: put_reg (11, val); break; case sim_rx_r12_regnum: put_reg (12, val); break; case sim_rx_r13_regnum: put_reg (13, val); break; case sim_rx_r14_regnum: put_reg (14, val); break; case sim_rx_r15_regnum: put_reg (15, val); break; case sim_rx_isp_regnum: put_reg (isp, val); break; case sim_rx_usp_regnum: put_reg (usp, val); break; case sim_rx_intb_regnum: put_reg (intb, val); break; case sim_rx_pc_regnum: put_reg (pc, val); break; case sim_rx_ps_regnum: put_reg (psw, val); break; case sim_rx_bpc_regnum: put_reg (bpc, val); break; case sim_rx_bpsw_regnum: put_reg (bpsw, val); break; case sim_rx_fintv_regnum: put_reg (fintv, val); break; case sim_rx_fpsw_regnum: put_reg (fpsw, val); break; default: fprintf (stderr, "rx minisim: unrecognized register number: %d\n", regno); return -1; } return size; }
int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) { size_t size; DI val; check_desc (sd); if (!check_regno (regno)) return 0; size = reg_size (regno); if (length != size) return 0; switch (regno) { case sim_rx_r0_regnum: val = get_reg (0); break; case sim_rx_r1_regnum: val = get_reg (1); break; case sim_rx_r2_regnum: val = get_reg (2); break; case sim_rx_r3_regnum: val = get_reg (3); break; case sim_rx_r4_regnum: val = get_reg (4); break; case sim_rx_r5_regnum: val = get_reg (5); break; case sim_rx_r6_regnum: val = get_reg (6); break; case sim_rx_r7_regnum: val = get_reg (7); break; case sim_rx_r8_regnum: val = get_reg (8); break; case sim_rx_r9_regnum: val = get_reg (9); break; case sim_rx_r10_regnum: val = get_reg (10); break; case sim_rx_r11_regnum: val = get_reg (11); break; case sim_rx_r12_regnum: val = get_reg (12); break; case sim_rx_r13_regnum: val = get_reg (13); break; case sim_rx_r14_regnum: val = get_reg (14); break; case sim_rx_r15_regnum: val = get_reg (15); break; case sim_rx_isp_regnum: val = get_reg (isp); break; case sim_rx_usp_regnum: val = get_reg (usp); break; case sim_rx_intb_regnum: val = get_reg (intb); break; case sim_rx_pc_regnum: val = get_reg (pc); break; case sim_rx_ps_regnum: val = get_reg (psw); break; case sim_rx_bpc_regnum: val = get_reg (bpc); break; case sim_rx_bpsw_regnum: val = get_reg (bpsw); break; case sim_rx_fintv_regnum: val = get_reg (fintv); break; case sim_rx_fpsw_regnum: val = get_reg (fpsw); break; case sim_rx_acc_regnum: val = ((DI) get_reg (acchi) << 32) | get_reg (acclo); break; default: fprintf (stderr, "rx minisim: unrecognized register number: %d\n", regno); return -1; } if (rx_big_endian) put_be (buf, length, val); else put_le (buf, length, val); return size; }
BOOT_CODE pptr_t alloc_region(word_t size_bits) { word_t i; word_t reg_index = 0; /* gcc cannot work out that this will not be used uninitialized */ region_t reg = REG_EMPTY; region_t rem_small = REG_EMPTY; region_t rem_large = REG_EMPTY; region_t new_reg; region_t new_rem_small; region_t new_rem_large; /* Search for a freemem region that will be the best fit for an allocation. We favour allocations * that are aligned to either end of the region. If an allocation must split a region we favour * an unbalanced split. In both cases we attempt to use the smallest region possible. In general * this means we aim to make the size of the smallest remaining region smaller (ideally zero) * followed by making the size of the largest remaining region smaller */ for (i = 0; i < MAX_NUM_FREEMEM_REG; i++) { /* Determine whether placing the region at the start or the end will create a bigger left over region */ if (ROUND_UP(ndks_boot.freemem[i].start, size_bits) - ndks_boot.freemem[i].start < ndks_boot.freemem[i].end - ROUND_DOWN(ndks_boot.freemem[i].end, size_bits)) { new_reg.start = ROUND_UP(ndks_boot.freemem[i].start, size_bits); new_reg.end = new_reg.start + BIT(size_bits); } else { new_reg.end = ROUND_DOWN(ndks_boot.freemem[i].end, size_bits); new_reg.start = new_reg.end - BIT(size_bits); } if (new_reg.end > new_reg.start && new_reg.start >= ndks_boot.freemem[i].start && new_reg.end <= ndks_boot.freemem[i].end) { if (new_reg.start - ndks_boot.freemem[i].start < ndks_boot.freemem[i].end - new_reg.end) { new_rem_small.start = ndks_boot.freemem[i].start; new_rem_small.end = new_reg.start; new_rem_large.start = new_reg.end; new_rem_large.end = ndks_boot.freemem[i].end; } else { new_rem_large.start = ndks_boot.freemem[i].start; new_rem_large.end = new_reg.start; new_rem_small.start = new_reg.end; new_rem_small.end = ndks_boot.freemem[i].end; } if ( is_reg_empty(reg) || (reg_size(new_rem_small) < reg_size(rem_small)) || (reg_size(new_rem_small) == reg_size(rem_small) && reg_size(new_rem_large) < reg_size(rem_large)) ) { reg = new_reg; rem_small = new_rem_small; rem_large = new_rem_large; reg_index = i; } } } if (is_reg_empty(reg)) { printf("Kernel init failing: not enough memory\n"); return 0; } /* Remove the region in question */ ndks_boot.freemem[reg_index] = REG_EMPTY; /* Add the remaining regions in largest to smallest order */ insert_region(rem_large); if (!insert_region(rem_small)) { printf("alloc_region(): wasted 0x%lx bytes due to alignment, try to increase MAX_NUM_FREEMEM_REG\n", (word_t)(rem_small.end - rem_small.start)); } return reg.start; }