static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool readonly, bool autocleanup,
bool round)
{
void *virt_addr;
uintptr_t offset = 0;
if (len == 0) {
msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr);
return ERROR_PTR;
}
if (round)
offset = round_to_page_boundaries(&phys_addr, &len);
if (readonly)
virt_addr = sys_physmap_ro_cached(phys_addr, len);
else
virt_addr = sys_physmap_rw_uncached(phys_addr, len);
if (ERROR_PTR == virt_addr) {
if (NULL == descr)
descr = "memory";
msg_perr("Error accessing %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n",
descr, len, PRIxPTR_WIDTH, phys_addr);
msg_perr(MEM_DEV " mmap failed: %s\n", strerror(errno));
#ifdef __linux__
if (EINVAL == errno) {
msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n");
msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n");
msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n");
msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n");
msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n");
}
#elif defined (__OpenBSD__)
msg_perr("Please set securelevel=-1 in /etc/rc.securelevel "
"and reboot, or reboot into\n"
"single user mode.\n");
#endif
return ERROR_PTR;
}
if (autocleanup) {
struct undo_physmap_data *d = malloc(sizeof(struct undo_physmap_data));
if (d == NULL) {
msg_perr("%s: Out of memory!\n", __func__);
physunmap(virt_addr, len);
return ERROR_PTR;
}
d->virt_addr = virt_addr;
d->len = len;
if (register_shutdown(undo_physmap, d) != 0) {
msg_perr("%s: Could not register shutdown function!\n", __func__);
physunmap(virt_addr, len);
return ERROR_PTR;
}
}
return virt_addr + offset;
}
int gfxnvidia_init(void)
{
uint32_t reg32;
if (rget_io_perms())
return 1;
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);
io_base_addr += 0x300000;
msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
/* Must be done before rpci calls. */
if (register_shutdown(gfxnvidia_shutdown, NULL))
return 1;
/* Allow access to flash interface (will disable screen). */
reg32 = pci_read_long(pcidev_dev, 0x50);
reg32 &= ~(1 << 0);
rpci_write_long(pcidev_dev, 0x50, reg32);
/* Write/erase doesn't work. */
programmer_may_write = 0;
register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
return 0;
}
int nicrealtek_init(void)
{
struct pci_dev *dev = NULL;
if (rget_io_perms())
return 1;
dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0);
if (!dev)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
/* Beware, this ignores the vendor ID! */
switch (dev->device_id) {
case 0x8139: /* RTL8139 */
case 0x1211: /* SMC 1211TX */
default:
bios_rom_addr = 0xD4;
bios_rom_data = 0xD7;
break;
case 0x8169: /* RTL8169 */
bios_rom_addr = 0x30;
bios_rom_data = 0x33;
break;
}
if (register_shutdown(nicrealtek_shutdown, NULL))
return 1;
register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
return 0;
}
int nicintel_init(void)
{
uintptr_t addr;
/* Needed only for PCI accesses on some platforms.
* FIXME: Refactor that into get_mem_perms/rget_io_perms/get_pci_perms?
*/
if (rget_io_perms())
return 1;
/* No need to check for errors, pcidev_init() will not return in case
* of errors.
* FIXME: BAR2 is not available if the device uses the CardBus function.
*/
addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);
nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
if (nicintel_bar == ERROR_PTR)
goto error_out_unmap;
/* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0);
/* FIXME: This is not an aligned mapping. Use 4k? */
nicintel_control_bar = physmap("Intel NIC control/status reg",
addr, NICINTEL_CONTROL_MEMMAP_SIZE);
if (nicintel_control_bar == ERROR_PTR)
goto error_out;
if (register_shutdown(nicintel_shutdown, NULL))
return 1;
/* FIXME: This register is pretty undocumented in all publicly available
* documentation from Intel. Let me quote the complete info we have:
* "Flash Control Register: The Flash Control register allows the CPU to
* enable writes to an external Flash. The Flash Control Register is a
* 32-bit field that allows access to an external Flash device."
* Ah yes, we also know where it is, but we have absolutely _no_ idea
* what we should do with it. Write 0x0001 because we have nothing
* better to do with our time.
*/
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
return 0;
error_out_unmap:
physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
error_out:
pci_cleanup(pacc);
return 1;
}
int pci_init_common(void)
{
if (pacc != NULL) {
msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n"
"Please report a bug at [email protected]\n", __func__);
return 1;
}
pacc = pci_alloc(); /* Get the pci_access structure */
pci_init(pacc); /* Initialize the PCI library */
if (register_shutdown(pcidev_shutdown, NULL))
return 1;
pci_scan_bus(pacc); /* We want to get the list of devices */
return 0;
}
int ogp_spi_init(void)
{
struct pci_dev *dev = NULL;
char *type;
type = extract_programmer_param("rom");
if (!type) {
msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
"which flashchip you want to access.\n");
return 1;
} else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_BPROM_SI;
ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_BPROM_SCK;
} else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_CPROM_SI;
ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_CPROM_SCK;
} else {
msg_perr("Invalid or missing rom= parameter.\n");
return 1;
}
if (rget_io_perms())
return 1;
dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
if (!dev)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
ogp_spibar = physmap("OGP registers", io_base_addr, 4096);
if (register_shutdown(ogp_spi_shutdown, NULL))
return 1;
if (bitbang_spi_init(&bitbang_spi_master_ogp))
return 1;
return 0;
}
static int it85xx_spi_common_init(struct superio s)
{
chipaddr base;
msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
s.vendor);
if (register_shutdown(it85xx_shutdown, NULL))
return 1;
#ifdef LPC_IO
/* Get LPCPNP of SHM. That's big-endian */
sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
sio_read(s.port, SHM_IO_BAR1);
msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
shm_io_base);
/* These pointers are not used directly. They will be send to EC's
* register for indirect access. */
base = 0xFFFFF000;
ce_high = ((unsigned char*)base) + 0xE00; /* 0xFFFFFE00 */
ce_low = ((unsigned char*)base) + 0xD00; /* 0xFFFFFD00 */
/* pre-set indirect-access registers since in most of cases they are
* 0xFFFFxx00. */
INDIRECT_A0(shm_io_base, base & 0xFF);
INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
INDIRECT_A3(shm_io_base, (base >> 24));
#endif
#ifdef LPC_MEMORY
base = (chipaddr)programmer_map_flash_region("it85 communication",
0xFFFFF000, 0x1000);
msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
(unsigned int)base);
ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */
ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */
#endif
return 0;
}
/* Get I/O permissions with automatic permission release on shutdown. */
int rget_io_perms(void)
{
#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
#if defined (__sun)
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif IS_BSD
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
#elif IS_LINUX || IS_MACOSX
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
"You need to be root.\n", strerror(errno));
#if defined (__OpenBSD__)
msg_perr("Please set securelevel=-1 in /etc/rc.securelevel and reboot, or reboot into \n");
msg_perr("single user mode.\n");
#endif
return 1;
} else {
register_shutdown(release_io_perms, NULL);
}
#else
/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
#endif
return 0;
}
void mmio_writeb(uint8_t val, void *addr)
{
*(volatile uint8_t *) addr = val;
sync_primitive();
}
void mmio_writew(uint16_t val, void *addr)
{
*(volatile uint16_t *) addr = val;
sync_primitive();
}
int jlink_spi_init(void)
{
char *arg;
unsigned long speed = 0;
register_shutdown(jlink_spi_shutdown, NULL);
arg = extract_programmer_param("spispeed");
if (arg) {
char *endptr;
errno = 0;
speed = strtoul(arg, &endptr, 10);
if (*endptr != '\0' || errno != 0) {
msg_perr("Invalid SPI speed specified: %s.\n", arg);
free(arg);
return 1;
}
if (speed < 1) {
msg_perr("SPI speed must be at least 1 kHz.\n");
free(arg);
return 1;
}
}
free(arg);
int ret;
bool use_serial_number;
uint32_t serial_number;
arg = extract_programmer_param("serial");
if (arg) {
if (!strlen(arg)) {
msg_perr("Emptpy serial number specified.\n");
free(arg);
return 1;
}
ret = jaylink_parse_serial_number(arg, &serial_number);
if (ret == JAYLINK_ERR) {
msg_perr("Invalid serial number specified: %s.\n", arg);
free(arg);
return 1;
} if (ret != JAYLINK_OK) {
msg_perr("jaylink_parse_serial_number() failed: %s.\n", jaylink_strerror(ret));
free(arg);
return 1;
}
use_serial_number = true;
} else {
use_serial_number = false;
}
free(arg);
reset_cs = true;
arg = extract_programmer_param("cs");
if (arg) {
if (!strcasecmp(arg, "reset")) {
reset_cs = true;
} else if (!strcasecmp(arg, "trst")) {
reset_cs = false;
} else {
msg_perr("Invalid chip select pin specified: '%s'.\n", arg);
free(arg);
return 1;
}
}
free(arg);
if (reset_cs)
msg_pdbg("Using RESET as chip select signal.\n");
else
msg_pdbg("Using TRST as chip select signal.\n");
ret = jaylink_init(&jaylink_ctx);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_init() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
ret = jaylink_discovery_scan(jaylink_ctx, 0);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_discover_scan() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
struct jaylink_device **devs;
ret = jaylink_get_devices(jaylink_ctx, &devs, NULL);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_devices() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (!use_serial_number)
msg_pdbg("No device selected, using first device.\n");
size_t i;
struct jaylink_device *dev;
bool device_found = false;
for (i = 0; devs[i]; i++) {
if (use_serial_number) {
uint32_t tmp;
ret = jaylink_device_get_serial_number(devs[i], &tmp);
if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
continue;
} else if (ret != JAYLINK_OK) {
msg_pwarn("jaylink_device_get_serial_number() failed: %s.\n",
jaylink_strerror(ret));
continue;
}
if (serial_number != tmp)
continue;
}
ret = jaylink_open(devs[i], &jaylink_devh);
if (ret == JAYLINK_OK) {
dev = devs[i];
device_found = true;
break;
}
jaylink_devh = NULL;
}
jaylink_free_devices(devs, true);
if (!device_found) {
msg_perr("No J-Link device found.\n");
return 1;
}
size_t length;
char *firmware_version;
ret = jaylink_get_firmware_version(jaylink_devh, &firmware_version,
&length);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_firmware_version() failed: %s.\n", jaylink_strerror(ret));
return 1;
} else if (length > 0) {
msg_pdbg("Firmware: %s\n", firmware_version);
free(firmware_version);
}
ret = jaylink_device_get_serial_number(dev, &serial_number);
if (ret == JAYLINK_OK) {
msg_pdbg("S/N: %" PRIu32 "\n", serial_number);
} else if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
msg_pdbg("S/N: N/A\n");
} else {
msg_perr("jaylink_device_get_serial_number() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
uint8_t caps[JAYLINK_DEV_EXT_CAPS_SIZE];
memset(caps, 0, sizeof(caps));
ret = jaylink_get_caps(jaylink_devh, caps);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_caps() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_EXT_CAPS)) {
ret = jaylink_get_extended_caps(jaylink_devh, caps);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_available_interfaces() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
}
uint32_t ifaces;
ret = jaylink_get_available_interfaces(jaylink_devh, &ifaces);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_available_interfaces() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (!(ifaces & (1 << JAYLINK_TIF_JTAG))) {
msg_perr("Device does not support JTAG interface.\n");
return 1;
}
ret = jaylink_select_interface(jaylink_devh, JAYLINK_TIF_JTAG, NULL);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_select_interface() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
struct jaylink_hardware_status hwstat;
ret = jaylink_get_hardware_status(jaylink_devh, &hwstat);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_hardware_status() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
msg_pdbg("VTarget: %u.%03u V\n", hwstat.target_voltage / 1000,
hwstat.target_voltage % 1000);
if (hwstat.target_voltage < MIN_TARGET_VOLTAGE) {
msg_perr("Target voltage is below %u.%03u V. You need to attach VTref to the I/O voltage of "
"the chip.\n", MIN_TARGET_VOLTAGE / 1000, MIN_TARGET_VOLTAGE % 1000);
return 1;
}
struct jaylink_speed device_speeds;
device_speeds.freq = DEFAULT_FREQ;
device_speeds.div = DEFAULT_FREQ_DIV;
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_SPEEDS)) {
ret = jaylink_get_speeds(jaylink_devh, &device_speeds);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_speeds() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
}
device_speeds.freq /= 1000;
msg_pdbg("Maximum SPI speed: %" PRIu32 " kHz\n", device_speeds.freq / device_speeds.div);
if (!speed) {
speed = device_speeds.freq / device_speeds.div;
msg_pdbg("SPI speed not specified, using %lu kHz.\n", speed);
}
if (speed > (device_speeds.freq / device_speeds.div)) {
msg_perr("Specified SPI speed of %lu kHz is too high. Maximum is %" PRIu32 " kHz.\n", speed,
device_speeds.freq / device_speeds.div);
return 1;
}
ret = jaylink_set_speed(jaylink_devh, speed);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_set_speed() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
msg_pdbg("SPI speed: %lu kHz\n", speed);
/* Ensure that the CS signal is not active initially. */
if (!deassert_cs())
return 1;
register_spi_master(&spi_master_jlink_spi);
return 0;
}
int pickit2_spi_init(void)
{
unsigned int usedevice = 0; // FIXME: allow to select one of multiple devices
uint8_t buf[CMD_LENGTH] = {
CMD_EXEC_SCRIPT,
10, /* Script length */
SCR_SET_PINS,
2, /* Bit-0=0(PDC Out), Bit-1=1(PGD In), Bit-2=0(PDC LL), Bit-3=0(PGD LL) */
SCR_SET_AUX,
0, /* Bit-0=0(Aux Out), Bit-1=0(Aux LL) */
SCR_VDD_ON,
SCR_MCLR_GND_OFF, /* Let CS# float */
SCR_VPP_PWM_ON,
SCR_VPP_ON, /* Pull CS# high */
SCR_BUSY_LED_ON,
CMD_CLR_DLOAD_BUFF,
CMD_CLR_ULOAD_BUFF,
CMD_END_OF_BUFFER
};
int spispeed_idx = 0;
char *spispeed = extract_programmer_param("spispeed");
if (spispeed != NULL) {
int i = 0;
for (; spispeeds[i].name; i++) {
if (strcasecmp(spispeeds[i].name, spispeed) == 0) {
spispeed_idx = i;
break;
}
}
if (spispeeds[i].name == NULL) {
msg_perr("Error: Invalid 'spispeed' value.\n");
free(spispeed);
return 1;
}
free(spispeed);
}
int millivolt = 3500;
char *voltage = extract_programmer_param("voltage");
if (voltage != NULL) {
millivolt = parse_voltage(voltage);
free(voltage);
if (millivolt < 0)
return 1;
}
/* Here comes the USB stuff */
usb_init();
(void)usb_find_busses();
(void)usb_find_devices();
struct usb_device *dev = get_device_by_vid_pid(PICKIT2_VID, PICKIT2_PID, usedevice);
if (dev == NULL) {
msg_perr("Could not find a PICkit2 on USB!\n");
return 1;
}
msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct);
pickit2_handle = usb_open(dev);
int ret = usb_set_configuration(pickit2_handle, 1);
if (ret != 0) {
msg_perr("Could not set USB device configuration: %i %s\n", ret, usb_strerror());
if (usb_close(pickit2_handle) != 0)
msg_perr("Could not close USB device!\n");
return 1;
}
ret = usb_claim_interface(pickit2_handle, 0);
if (ret != 0) {
msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, usb_strerror());
if (usb_close(pickit2_handle) != 0)
msg_perr("Could not close USB device!\n");
return 1;
}
if (register_shutdown(pickit2_shutdown, NULL) != 0) {
return 1;
}
if (pickit2_get_firmware_version()) {
return 1;
}
/* Command Set SPI Speed */
if (pickit2_set_spi_speed(spispeed_idx)) {
return 1;
}
/* Command Set SPI Voltage */
msg_pdbg("Setting voltage to %i mV.\n", millivolt);
if (pickit2_set_spi_voltage(millivolt) != 0) {
return 1;
}
/* Perform basic setup.
* Configure pin directions and logic levels, turn Vdd on, turn busy LED on and clear buffers. */
ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT);
if (ret != CMD_LENGTH) {
msg_perr("Command Setup failed (%s)!\n", usb_strerror());
return 1;
}
register_spi_master(&spi_master_pickit2);
return 0;
}
/* Returns 0 upon success, a negative number upon errors. */
int mstarddc_spi_init(void)
{
int ret = 0;
// Get device, address from command-line
char *i2c_device = extract_programmer_param("dev");
if (i2c_device != NULL && strlen(i2c_device) > 0) {
char *i2c_address = strchr(i2c_device, ':');
if (i2c_address != NULL) {
*i2c_address = '\0';
i2c_address++;
}
if (i2c_address == NULL || strlen(i2c_address) == 0) {
msg_perr("Error: no address specified.\n"
"Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n");
ret = -1;
goto out;
}
mstarddc_addr = strtol(i2c_address, NULL, 16); // FIXME: error handling
} else {
msg_perr("Error: no device specified.\n"
"Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n");
ret = -1;
goto out;
}
msg_pinfo("Info: Will try to use device %s and address 0x%02x.\n", i2c_device, mstarddc_addr);
// Get noreset=1 option from command-line
char *noreset = extract_programmer_param("noreset");
if (noreset != NULL && noreset[0] == '1')
mstarddc_doreset = 0;
free(noreset);
msg_pinfo("Info: Will %sreset the device at the end.\n", mstarddc_doreset ? "" : "NOT ");
// Open device
if ((mstarddc_fd = open(i2c_device, O_RDWR)) < 0) {
switch (errno) {
case EACCES:
msg_perr("Error opening %s: Permission denied.\n"
"Please use sudo or run as root.\n",
i2c_device);
break;
case ENOENT:
msg_perr("Error opening %s: No such file.\n"
"Please check you specified the correct device.\n",
i2c_device);
break;
default:
msg_perr("Error opening %s: %s.\n", i2c_device, strerror(errno));
}
ret = -1;
goto out;
}
// Set slave address
if (ioctl(mstarddc_fd, I2C_SLAVE, mstarddc_addr) < 0) {
msg_perr("Error setting slave address 0x%02x: errno %d.\n",
mstarddc_addr, errno);
ret = -1;
goto out;
}
// Enable ISP mode
uint8_t cmd[5] = { 'M', 'S', 'T', 'A', 'R' };
if (write(mstarddc_fd, cmd, 5) < 0) {
int enable_err = errno;
uint8_t end_cmd = MSTARDDC_SPI_END;
// Assume device is already in ISP mode, try to send END command
if (write(mstarddc_fd, &end_cmd, 1) < 0) {
msg_perr("Error enabling ISP mode: errno %d & %d.\n"
"Please check that device (%s) and address (0x%02x) are correct.\n",
enable_err, errno, i2c_device, mstarddc_addr);
ret = -1;
goto out;
}
}
// Register shutdown function
register_shutdown(mstarddc_spi_shutdown, NULL);
// Register programmer
register_spi_master(&spi_master_mstarddc);
out:
free(i2c_device);
return ret;
}
/** Start up transport. Read configuration, register callbacks. */
void icqtrans(instance i, xmlnode x)
{
iti ti;
pool p = i->p;
xmlnode config;
xmlnode cur;
int check;
log_debug(ZONE,"ICQ Transport, initializing for section '%s'",i->id);
/* create new transport instance */
ti = pmalloco(p,sizeof(_iti));
ti->i = i;
ti->xc = xdb_cache(i);
config = xdb_get(ti->xc,jid_new(xmlnode_pool(x),"config@-internal"),"jabber:config:icqtrans");
if (config == NULL)
{
log_error(i->id,"Configuration not found!");
return;
}
ti->registration_instructions = pstrdup(p,xmlnode_get_tag_data(config,"instructions"));
if (ti->registration_instructions == NULL)
{
log_debug(i->id,"Registration instructions not found");
}
ti->search_instructions = pstrdup(p,xmlnode_get_tag_data(config,"search"));
if (ti->search_instructions == NULL)
{
log_debug(i->id,"Search instructions not found");
}
ti->charset = pstrdup(p,xmlnode_get_tag_data(config,"charset"));
if (ti->charset == NULL)
{
log_debug(i->id,"Charset not specified, set default to %s ",DEFAULT_CHARSET);
ti->charset = pstrdup(p,DEFAULT_CHARSET);
}
_ucs2utf = iconv_open("UTF-8","UCS-2BE");
_win2utf = iconv_open("UTF-8",ti->charset);
if (_win2utf==(iconv_t)-1) {
ti->charset = pstrdup(p,DEFAULT_CHARSET);
_win2utf = iconv_open("UTF-8",ti->charset);
if (_win2utf==(iconv_t)-1) {
log_error(i->id,"Charset error!");
return;
}
}
_utf2win = iconv_open(ti->charset,"UTF-8");
if (_utf2win ==(iconv_t)-1) {
ti->charset = pstrdup(p,DEFAULT_CHARSET);
_utf2win = iconv_open(ti->charset,"UTF-8");
if (_utf2win ==(iconv_t)-1) {
log_error(i->id,"Charset error!");
return;
}
}
log_notice("config","charset %s",ti->charset);
ti->msg_chat = xmlnode_get_tag(config,"chat") ? 1 : 0;
if (ti->msg_chat) {
log_notice("config","chat messages enabled");
}
ti->web_aware = xmlnode_get_tag(config,"web") ? 1 : 0;
if (ti->web_aware) {
log_notice("config","web presence enabled");
}
ti->own_roster = xmlnode_get_tag(config,"own_roster") ? 1 : 0;
if (ti->own_roster) {
log_notice("config","JIT will use own roster");
}
ti->no_jabber_roster = xmlnode_get_tag(config,"no_jabber_roster") ? 1 : 0;
if (ti->no_jabber_roster) {
log_notice("config","JIT willn't get users from jabber roster");
}
ti->no_x_data = xmlnode_get_tag(config,"no_xdata") ? 1 : 0;
if (ti->no_x_data) {
log_notice("config","JIT will not use xdata");
}
cur = xmlnode_get_tag(config,"sms");
if (cur) {
ti->sms_id = pstrdup(p,xmlnode_get_tag_data(cur,"host"));
if (ti->sms_id) {
ti->sms_show = jit_show2status(xmlnode_get_tag_data(cur,"show"));
if (ti->sms_show==ICQ_STATUS_NOT_IN_LIST) {
ti->sms_show = ICQ_STATUS_ONLINE;
}
log_notice("config","sms host %s show: %d",ti->sms_id,ti->sms_show);
ti->sms_status = pstrdup(p,xmlnode_get_tag_data(cur,"status"));
if (ti->sms_status) {
log_debug(ZONE,"sms st %s ",ti->sms_status);
}
ti->sms_name = pstrdup(p,xmlnode_get_tag_data(cur,"name"));
if (ti->sms_name) {
log_debug(ZONE,"sms name %s",ti->sms_name);
}
}
}
ti->count_file = pstrdup(p,xmlnode_get_tag_data(config,"user_count_file"));
if (ti->count_file == NULL) {
ti->count_file = "icqcount";
}
log_notice("config","Using %s as count log file",ti->count_file);
for (cur = xmlnode_get_firstchild(xmlnode_get_tag(config,"server"));
cur != NULL;
cur = xmlnode_get_nextsibling(cur)) {
char * port;
char * host;
if (xmlnode_get_type(cur) != NTYPE_TAG) continue;
if ((port = xmlnode_get_attrib(cur,"port")) == NULL) continue;
if ((host = xmlnode_get_data(cur)) == NULL) continue;
ti->auth_hosts[ti->auth_hosts_count] = pstrdup(p,host);
ti->auth_ports[ti->auth_hosts_count] = j_atoi(port,5190);
log_debug(ZONE,"Host %s port %d at pos %d",
ti->auth_hosts[ti->auth_hosts_count],
ti->auth_ports[ti->auth_hosts_count],
ti->auth_hosts_count);
ti->auth_hosts_count++;
if (ti->auth_hosts_count >= MAX_AUTH_HOSTS) break;
}
if (ti->auth_hosts_count == 0) {
log_alert("err","No hosts to auth icq client !. Using default");
ti->auth_hosts[ti->auth_hosts_count] = pstrdup(p,"205.188.179.233");
ti->auth_ports[ti->auth_hosts_count] = 5190;
ti->auth_hosts_count++;
}
/* add queue for unknown packets */
ti->q = mtq_new(i->p);
ti->sessions = wpxhash_new(j_atoi(xmlnode_get_tag_data(config,"prime"),509));
ti->sessions_alt = wpxhash_new(j_atoi(xmlnode_get_tag_data(config,"prime"),509));
SEM_INIT(ti->sessions_sem);
ti->vcard = xmlnode_new_tag_pool(p,"vCard");
xmlnode_put_attrib(ti->vcard,"xmlns",NS_VCARD);
xmlnode_insert_node(ti->vcard,xmlnode_get_firstchild(xmlnode_get_tag(config,"vCard")));
/* default 5 hours */
ti->session_timeout = j_atoi(xmlnode_get_tag_data(config,"session_timeout"),18000);
log_notice("config","session_timeout in sec : %d",ti->session_timeout);
ti->reconnect = j_atoi(xmlnode_get_tag_data(config,"reconnects"),0);
log_notice("config","Number of reconnects for session %d",ti->reconnect);
check = j_atoi(xmlnode_get_tag_data(config,"session_check"),10);
log_notice("config","JIT will check session every %d sec",check);
// ti->admin = xmlnode_dup(xmlnode_get_tag(config,"admin"));
ti->start = time(NULL);
/* Register callbacks */
register_phandler(i,o_DELIVER,it_receive,(void *) ti);
register_shutdown(it_shutdown,(void *) ti);
/* Start up heartbeat thread */
register_beat(check,it_sessions_check,(void *) ti);
xmlnode_free(config);
}
int linux_spi_init(void)
{
char *p, *endp, *dev;
uint32_t speed = 0;
/* FIXME: make the following configurable by CLI options. */
/* SPI mode 0 (beware this also includes: MSB first, CS active low and others */
const uint8_t mode = SPI_MODE_0;
const uint8_t bits = 8;
dev = extract_programmer_param("dev");
if (!dev || !strlen(dev)) {
msg_perr("No SPI device given. Use flashrom -p "
"linux_spi:dev=/dev/spidevX.Y\n");
return 1;
}
p = extract_programmer_param("speed");
if (p && strlen(p)) {
speed = (uint32_t)strtoul(p, &endp, 10) * 1024;
if (p == endp) {
msg_perr("%s: invalid clock: %s kHz\n", __func__, p);
return 1;
}
}
msg_pdbg("Using device %s\n", dev);
if ((fd = open(dev, O_RDWR)) == -1) {
msg_perr("%s: failed to open %s: %s\n", __func__,
dev, strerror(errno));
return 1;
}
if (register_shutdown(linux_spi_shutdown, NULL))
return 1;
/* We rely on the shutdown function for cleanup from here on. */
if (speed > 0) {
if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) {
msg_perr("%s: failed to set speed to %d Hz: %s\n",
__func__, speed, strerror(errno));
return 1;
}
msg_pdbg("Using %d kHz clock\n", speed);
}
if (ioctl(fd, SPI_IOC_WR_MODE, &mode) == -1) {
msg_perr("%s: failed to set SPI mode to 0x%02x: %s\n",
__func__, mode, strerror(errno));
return 1;
}
if (ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits) == -1) {
msg_perr("%s: failed to set the number of bits per SPI word to %u: %s\n",
__func__, bits == 0 ? 8 : bits, strerror(errno));
return 1;
}
register_spi_programmer(&spi_programmer_linux);
return 0;
}
int internal_init(void)
{
#if __FLASHROM_LITTLE_ENDIAN__
int ret = 0;
#endif
int force_laptop = 0;
int not_a_laptop = 0;
const char *board_vendor = NULL;
const char *board_model = NULL;
#if defined (__i386__) || defined (__x86_64__) || defined (__arm__)
const char *cb_vendor = NULL;
const char *cb_model = NULL;
#endif
char *arg;
arg = extract_programmer_param("boardenable");
if (arg && !strcmp(arg,"force")) {
force_boardenable = 1;
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for boardenable.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for boardenable: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("boardmismatch");
if (arg && !strcmp(arg,"force")) {
force_boardmismatch = 1;
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for boardmismatch.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for boardmismatch: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("laptop");
if (arg && !strcmp(arg, "force_I_want_a_brick"))
force_laptop = 1;
else if (arg && !strcmp(arg, "this_is_not_a_laptop"))
not_a_laptop = 1;
else if (arg && !strlen(arg)) {
msg_perr("Missing argument for laptop.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for laptop: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("mainboard");
if (arg && strlen(arg)) {
if (board_parse_parameter(arg, &board_vendor, &board_model)) {
free(arg);
return 1;
}
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for mainboard.\n");
free(arg);
return 1;
}
free(arg);
if (rget_io_perms())
return 1;
if (register_shutdown(internal_shutdown, NULL))
return 1;
/* Default to Parallel/LPC/FWH flash devices. If a known host controller
* is found, the host controller init routine sets the
* internal_buses_supported bitfield.
*/
internal_buses_supported = BUS_NONSPI;
/* Initialize PCI access for flash enables */
if (pci_init_common() != 0)
return 1;
if (processor_flash_enable()) {
msg_perr("Processor detection/init failed.\n"
"Aborting.\n");
return 1;
}
#if defined(__i386__) || defined(__x86_64__) || defined (__arm__)
if ((cb_parse_table(&cb_vendor, &cb_model) == 0) && (board_vendor != NULL) && (board_model != NULL)) {
if (strcasecmp(board_vendor, cb_vendor) || strcasecmp(board_model, cb_model)) {
msg_pwarn("Warning: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n"
" match the current coreboot IDs of the mainboard (%s:%s).\n",
board_vendor, board_model, cb_vendor, cb_model);
if (!force_boardmismatch)
return 1;
msg_pinfo("Continuing anyway.\n");
}
}
#endif
#if defined(__i386__) || defined(__x86_64__)
dmi_init();
/* In case Super I/O probing would cause pretty explosions. */
board_handle_before_superio();
/* Probe for the Super I/O chip and fill global struct superio. */
probe_superio();
#else
/* FIXME: Enable cbtable searching on all non-x86 platforms supported
* by coreboot.
* FIXME: Find a replacement for DMI on non-x86.
* FIXME: Enable Super I/O probing once port I/O is possible.
*/
#endif
/* Check laptop whitelist. */
board_handle_before_laptop();
/* Warn if a non-whitelisted laptop is detected. */
if (is_laptop && !laptop_ok) {
msg_perr("========================================================================\n");
if (is_laptop == 1) {
msg_perr("WARNING! You seem to be running flashrom on an unsupported laptop.\n");
} else {
msg_perr("WARNING! You may be running flashrom on an unsupported laptop. We could\n"
"not detect this for sure because your vendor has not setup the SMBIOS\n"
"tables correctly. You can enforce execution by adding\n"
"'-p internal:laptop=this_is_not_a_laptop' to the command line, but\n"
"please read the following warning if you are not sure.\n\n");
}
msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n"
"recommend to use the vendor flashing utility. The embedded controller\n"
"(EC) in these machines often interacts badly with flashing.\n"
"See the manpage and http://www.flashrom.org/Laptops for details.\n\n"
"If flash is shared with the EC, erase is guaranteed to brick your laptop\n"
"and write may brick your laptop.\n"
"Read and probe may irritate your EC and cause fan failure, backlight\n"
"failure and sudden poweroff.\n"
"You have been warned.\n"
"========================================================================\n");
if (force_laptop || (not_a_laptop && (is_laptop == 2))) {
msg_perr("Proceeding anyway because user forced us to.\n");
} else {
msg_perr("Aborting.\n");
return 1;
}
}
#if __FLASHROM_LITTLE_ENDIAN__
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
*/
ret = chipset_flash_enable();
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
} else if (ret == ERROR_FATAL)
return ret;
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
init_superio_ite();
#endif
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");
return 1;
}
#if defined(__i386__) || defined(__x86_64__) || defined (__mips)
register_par_master(&par_master_internal, internal_buses_supported);
return 0;
#else
msg_perr("Your platform is not supported yet for the internal "
"programmer due to missing\n"
"flash_base and top/bottom alignment information.\n"
"Aborting.\n");
return 1;
#endif
#else
/* FIXME: Remove this unconditional abort once all PCI drivers are
* converted to use little-endian accesses for memory BARs.
*/
msg_perr("Your platform is not supported yet for the internal "
"programmer because it has\n"
"not been converted from native endian to little endian "
"access yet.\n"
"Aborting.\n");
return 1;
#endif
}
