static int si544_set_muldiv(struct clk_si544 *data,
struct clk_si544_muldiv *settings)
{
int err;
u8 reg[6];
reg[0] = settings->hs_div;
reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4;
err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2);
if (err < 0)
return err;
reg[0] = settings->fb_div_frac;
reg[1] = settings->fb_div_frac >> 8;
reg[2] = settings->fb_div_frac >> 16;
reg[3] = settings->fb_div_frac >> 24;
reg[4] = settings->fb_div_int;
reg[5] = settings->fb_div_int >> 8;
/*
* Writing to SI544_REG_FBDIV40 triggers the clock change, so that
* must be written last
*/
return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6);
}
/* write reg val table using reg addr auto increment */
static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
const struct m88ds3103_reg_val *tab, int tab_len)
{
struct i2c_client *client = dev->client;
int ret, i, j;
u8 buf[83];
dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
if (tab_len > 86) {
ret = -EINVAL;
goto err;
}
for (i = 0, j = 0; i < tab_len; i++, j++) {
buf[j] = tab[i].val;
if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
!((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
if (ret)
goto err;
j = -1;
}
}
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int tps65910_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
unsigned char alarm_data[NUM_TIME_REGS];
struct tps65910 *tps = dev_get_drvdata(dev->parent);
int ret;
ret = tps65910_rtc_alarm_irq_enable(dev, 0);
if (ret)
return ret;
alarm_data[0] = bin2bcd(alm->time.tm_sec);
alarm_data[1] = bin2bcd(alm->time.tm_min);
alarm_data[2] = bin2bcd(alm->time.tm_hour);
alarm_data[3] = bin2bcd(alm->time.tm_mday);
alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
/* update all the alarm registers in one shot */
ret = regmap_bulk_write(tps->regmap, TPS65910_ALARM_SECONDS,
alarm_data, NUM_TIME_REGS);
if (ret) {
dev_err(dev, "rtc_set_alarm error %d\n", ret);
return ret;
}
if (alm->enabled)
ret = tps65910_rtc_alarm_irq_enable(dev, 1);
return ret;
}
static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct da9063_rtc *rtc = dev_get_drvdata(dev);
u8 data[RTC_DATA_LEN];
int ret;
da9063_tm_to_data(&alrm->time, data);
ret = da9063_rtc_stop_alarm(dev);
if (ret < 0) {
dev_err(dev, "Failed to stop alarm: %d\n", ret);
return ret;
}
ret = regmap_bulk_write(rtc->hw->regmap, rtc->alarm_start,
&data[rtc->data_start], rtc->alarm_len);
if (ret < 0) {
dev_err(dev, "Failed to write alarm: %d\n", ret);
return ret;
}
da9063_data_to_tm(data, &rtc->alarm_time);
if (alrm->enabled) {
ret = da9063_rtc_start_alarm(dev);
if (ret < 0) {
dev_err(dev, "Failed to start alarm: %d\n", ret);
return ret;
}
}
return ret;
}
static int imx_ocotp_write(struct device_d *dev, const int offset,
const void *val, int bytes)
{
struct ocotp_priv *priv = dev->parent->priv;
return regmap_bulk_write(priv->map, offset, val, bytes);
}
static int rc5t583_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev->parent);
unsigned char alarm_data[NUM_YAL_REGS];
int ret;
ret = rc5t583_rtc_alarm_irq_enable(dev, 0);
if (ret)
return ret;
alarm_data[0] = bin2bcd(alm->time.tm_min);
alarm_data[1] = bin2bcd(alm->time.tm_hour);
alarm_data[2] = bin2bcd(alm->time.tm_mday);
alarm_data[3] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[4] = bin2bcd(alm->time.tm_year - 100);
ret = regmap_bulk_write(rc5t583->regmap, RC5T583_RTC_AY_MIN, alarm_data,
NUM_YAL_REGS);
if (ret) {
dev_err(dev, "rtc_set_alarm error %d\n", ret);
return ret;
}
if (alm->enabled)
ret = rc5t583_rtc_alarm_irq_enable(dev, 1);
return ret;
}
static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max77686_rtc_tm_to_data(&alrm->time, data);
if (ret < 0)
return ret;
mutex_lock(&info->lock);
ret = max77686_rtc_stop_alarm(info);
if (ret < 0)
goto out;
ret = regmap_bulk_write(info->max77686->rtc_regmap,
MAX77686_ALARM1_SEC, data, RTC_NR_TIME);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
__func__, ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
if (ret < 0)
goto out;
if (alrm->enabled)
ret = max77686_rtc_start_alarm(info);
out:
mutex_unlock(&info->lock);
return ret;
}
static int ds1343_nvram_write(void *priv, unsigned int off, void *val,
size_t bytes)
{
struct ds1343_priv *ds1343 = priv;
return regmap_bulk_write(ds1343->map, DS1343_NVRAM + off, val, bytes);
}
static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max77686_rtc_tm_to_data(tm, data);
if (ret < 0)
return ret;
mutex_lock(&info->lock);
ret = regmap_bulk_write(info->max77686->rtc_regmap,
MAX77686_RTC_SEC, data, RTC_NR_TIME);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write time reg(%d)\n", __func__,
ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
out:
mutex_unlock(&info->lock);
return ret;
}
static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
int ret;
/*
* Year register is 8-bit wide and bcd-coded, i.e records values
* between 0 and 99. tm_year is an offset from 1900 and we are
* interested in the 2000-2099 range, so any value less than 100
* is invalid.
*/
if (tm->tm_year < 100)
return -EINVAL;
regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
mutex_lock(&data->lock);
ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
regs + ABB5ZES3_REG_RTC_SC,
ABB5ZES3_RTC_SEC_LEN);
mutex_unlock(&data->lock);
return ret;
}
/*
* Set alarm using timer watchdog (via timer A) mechanism. The function expects
* timer A interrupt to be disabled.
*/
static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
u8 secs)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABB5ZES3_TIMA_SEC_LEN];
u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
int ret = 0;
/* Program given number of seconds to Timer A registers */
sec_to_timer_a(secs, ®s[0], ®s[1]);
ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
ABB5ZES3_TIMA_SEC_LEN);
if (ret < 0) {
dev_err(dev, "%s: writing timer section failed\n", __func__);
goto err;
}
/* Configure Timer A as a watchdog timer */
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
mask, ABB5ZES3_REG_TIM_CLK_TAC1);
if (ret)
dev_err(dev, "%s: failed to update timer\n", __func__);
/* Record currently configured alarm is a timer */
data->timer_alarm = 1;
/* Enable or disable timer interrupt generation */
ret = _abb5zes3_rtc_update_timer(dev, alarm->enabled);
err:
return ret;
}
static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct mt6397_rtc *rtc = dev_get_drvdata(dev);
int ret;
u16 data[RTC_OFFSET_COUNT];
tm->tm_year -= RTC_MIN_YEAR_OFFSET;
tm->tm_mon++;
data[RTC_OFFSET_SEC] = tm->tm_sec;
data[RTC_OFFSET_MIN] = tm->tm_min;
data[RTC_OFFSET_HOUR] = tm->tm_hour;
data[RTC_OFFSET_DOM] = tm->tm_mday;
data[RTC_OFFSET_MTH] = tm->tm_mon;
data[RTC_OFFSET_YEAR] = tm->tm_year;
mutex_lock(&rtc->lock);
ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
data, RTC_OFFSET_COUNT);
if (ret < 0)
goto exit;
/* Time register write to hardware after call trigger function */
ret = mtk_rtc_write_trigger(rtc);
exit:
mutex_unlock(&rtc->lock);
return ret;
}
int max77693_bulk_write(struct regmap *map, u8 reg, int count, u8 *buf)
{
int ret;
ret = regmap_bulk_write(map, reg, buf, count);
return ret;
}
static int max8907_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct max8907_rtc *rtc = dev_get_drvdata(dev);
u8 regs[TIME_NUM];
tm_to_regs(tm, regs);
return regmap_bulk_write(rtc->regmap, MAX8907_REG_RTC_SEC, regs,
TIME_NUM);
}
static int it913x_sleep(struct dvb_frontend *fe)
{
struct it913x_dev *dev = fe->tuner_priv;
int ret, len;
dev_dbg(&dev->client->dev, "role %u\n", dev->role);
dev->active = false;
ret = regmap_bulk_write(dev->regmap, 0x80ec40, "\x00", 1);
if (ret)
goto err;
/*
* Writing '0x00' to master tuner register '0x80ec08' causes slave tuner
* communication lost. Due to that, we cannot put master full sleep.
*/
if (dev->role == IT913X_ROLE_DUAL_MASTER)
len = 4;
else
len = 15;
dev_dbg(&dev->client->dev, "role %u, len %d\n", dev->role, len);
ret = regmap_bulk_write(dev->regmap, 0x80ec02,
"\x3f\x1f\x3f\x3e\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
len);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec12, "\x00\x00\x00\x00", 4);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec17,
"\x00\x00\x00\x00\x00\x00\x00\x00\x00", 9);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec22,
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 10);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec20, "\x00", 1);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x80ec3f, "\x01", 1);
if (ret)
goto err;
return 0;
err:
dev_dbg(&dev->client->dev, "failed %d\n", ret);
return ret;
}
static int rv3029_write_regs(struct device *dev, u8 reg, u8 const buf[],
unsigned int len)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
if ((reg > RV3029_USR1_RAM_PAGE + 7) ||
(reg + len > RV3029_USR1_RAM_PAGE + 8))
return -EINVAL;
return regmap_bulk_write(rv3029->regmap, reg, buf, len);
}
static int imx_ocotp_set_mac(struct param_d *param, void *priv)
{
char buf[MAC_BYTES];
struct ocotp_priv_ethaddr *ethaddr = priv;
ethaddr->data->format_mac(buf, ethaddr->value,
OCOTP_MAC_TO_HW);
return regmap_bulk_write(ethaddr->map, ethaddr->offset,
buf, MAC_BYTES);
}
static void adv7511_set_config(struct drm_encoder *encoder, void *c)
{
struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
struct adv7511_video_config *config = c;
bool output_format_422, output_format_ycbcr;
unsigned int mode;
uint8_t infoframe[17];
if (config->hdmi_mode) {
mode = ADV7511_HDMI_CFG_MODE_HDMI;
switch (config->avi_infoframe.colorspace) {
case HDMI_COLORSPACE_YUV444:
output_format_422 = false;
output_format_ycbcr = true;
break;
case HDMI_COLORSPACE_YUV422:
output_format_422 = true;
output_format_ycbcr = true;
break;
default:
output_format_422 = false;
output_format_ycbcr = false;
break;
}
} else {
mode = ADV7511_HDMI_CFG_MODE_DVI;
output_format_422 = false;
output_format_ycbcr = false;
}
adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
adv7511_set_colormap(adv7511, config->csc_enable,
config->csc_coefficents,
config->csc_scaling_factor);
regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x81,
(output_format_422 << 7) | output_format_ycbcr);
regmap_update_bits(adv7511->regmap, ADV7511_REG_HDCP_HDMI_CFG,
ADV7511_HDMI_CFG_MODE_MASK, mode);
hdmi_avi_infoframe_pack(&config->avi_infoframe, infoframe,
sizeof(infoframe));
/* The AVI infoframe id is not configurable */
regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION,
infoframe + 1, sizeof(infoframe) - 1);
adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
}
static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct rtc_time *tm = &alm->time;
struct mt6397_rtc *rtc = dev_get_drvdata(dev);
int ret;
u16 data[RTC_OFFSET_COUNT];
tm->tm_year -= RTC_MIN_YEAR_OFFSET;
tm->tm_mon++;
data[RTC_OFFSET_SEC] = tm->tm_sec;
data[RTC_OFFSET_MIN] = tm->tm_min;
data[RTC_OFFSET_HOUR] = tm->tm_hour;
data[RTC_OFFSET_DOM] = tm->tm_mday;
data[RTC_OFFSET_MTH] = tm->tm_mon;
data[RTC_OFFSET_YEAR] = tm->tm_year;
mutex_lock(&rtc->lock);
if (alm->enabled) {
ret = regmap_bulk_write(rtc->regmap,
rtc->addr_base + RTC_AL_SEC,
data, RTC_OFFSET_COUNT);
if (ret < 0)
goto exit;
ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
RTC_AL_MASK_DOW);
if (ret < 0)
goto exit;
ret = regmap_update_bits(rtc->regmap,
rtc->addr_base + RTC_IRQ_EN,
RTC_IRQ_EN_ONESHOT_AL,
RTC_IRQ_EN_ONESHOT_AL);
if (ret < 0)
goto exit;
} else {
ret = regmap_update_bits(rtc->regmap,
rtc->addr_base + RTC_IRQ_EN,
RTC_IRQ_EN_ONESHOT_AL, 0);
if (ret < 0)
goto exit;
}
/* All alarm time register write to hardware after calling
* mtk_rtc_write_trigger. This can avoid race condition if alarm
* occur happen during writing alarm time register.
*/
ret = mtk_rtc_write_trigger(rtc);
exit:
mutex_unlock(&rtc->lock);
return ret;
}
static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
{
__be16 raw_val[3];
int ret;
int i;
/* Reset */
ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
if (ret)
return ret;
/* Turn on the Z-axis PLL */
ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
MPU3050_PWR_MGM_CLKSEL_MASK,
MPU3050_PWR_MGM_PLL_Z);
if (ret)
return ret;
/* Write calibration offset registers */
for (i = 0; i < 3; i++)
raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
sizeof(raw_val));
if (ret)
return ret;
/* Set low pass filter (sample rate), sync and full scale */
ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
mpu3050->fullscale << MPU3050_FS_SHIFT |
mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
if (ret)
return ret;
/* Set up sampling frequency */
ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
if (ret)
return ret;
/*
* Max 50 ms start-up time after setting DLPF_FS_SYNC
* according to the data sheet, then wait for the next sample
* at this frequency T = 1000/f ms.
*/
msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
return 0;
}
static int da9063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct da9063_rtc *rtc = dev_get_drvdata(dev);
u8 data[RTC_DATA_LEN];
int ret;
da9063_tm_to_data(tm, data);
ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_COUNT_S,
data, RTC_DATA_LEN);
if (ret < 0)
dev_err(dev, "Failed to set RTC time data: %d\n", ret);
return ret;
}
static int si2165_write(struct si2165_state *state, const u16 reg,
const u8 *src, const int count)
{
int ret;
if (debug & DEBUG_I2C_WRITE)
deb_i2c_write("reg: 0x%04x, data: %*ph\n", reg, count, src);
ret = regmap_bulk_write(state->regmap, reg, src, count);
if (ret)
dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
return ret;
}
static int imx_ocotp_set_mac(struct param_d *param, void *priv)
{
struct ocotp_priv *ocotp_priv = priv;
char buf[8];
int i, ret;
for (i = 0; i < 6; i++)
buf[5 - i] = ocotp_priv->ethaddr[i];
buf[6] = 0; buf[7] = 0;
ret = regmap_bulk_write(ocotp_priv->map, MAC_OFFSET, buf, MAC_BYTES);
if (ret < 0)
return ret;
return 0;
}
static int write_coeff_ram(struct snd_soc_codec *codec, u8 *coeff_ram,
unsigned int addr, unsigned int coeff_cnt)
{
struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec);
int cnt;
int trys;
int ret;
for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) {
for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
ret = snd_soc_read(codec, R_DACCRSTAT);
if (ret < 0) {
dev_err(codec->dev,
"Failed to read stat (%d)\n", ret);
return ret;
}
if (!ret)
break;
}
if (trys == DACCRSTAT_MAX_TRYS) {
ret = -EIO;
dev_err(codec->dev,
"dac coefficient write error (%d)\n", ret);
return ret;
}
ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr);
if (ret < 0) {
dev_err(codec->dev,
"Failed to write dac ram address (%d)\n", ret);
return ret;
}
ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL,
&coeff_ram[addr * COEFF_SIZE],
COEFF_SIZE);
if (ret < 0) {
dev_err(codec->dev,
"Failed to write dac ram (%d)\n", ret);
return ret;
}
}
return 0;
}
static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
{
u8 data[RTC_NR_TIME];
int ret;
struct rtc_time tm;
if (!mutex_is_locked(&info->lock))
dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
ret = max77686_rtc_update(info, MAX77686_RTC_READ);
if (ret < 0)
goto out;
ret = regmap_bulk_read(info->max77686->rtc_regmap,
MAX77686_ALARM1_SEC, data, RTC_NR_TIME);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
__func__, ret);
goto out;
}
max77686_rtc_data_to_tm(data, &tm, info->rtc_24hr_mode);
data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
if (data[RTC_MONTH] & 0xf)
data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_YEAR] & 0x7f)
data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_DATE] & 0x1f)
data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
ret = regmap_bulk_write(info->max77686->rtc_regmap,
MAX77686_ALARM1_SEC, data, RTC_NR_TIME);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
__func__, ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
out:
return ret;
}
static int ds1343_update_alarm(struct device *dev)
{
struct ds1343_priv *priv = dev_get_drvdata(dev);
unsigned int control, stat;
unsigned char buf[4];
int res = 0;
res = regmap_read(priv->map, DS1343_CONTROL_REG, &control);
if (res)
return res;
res = regmap_read(priv->map, DS1343_STATUS_REG, &stat);
if (res)
return res;
control &= ~(DS1343_A0IE);
stat &= ~(DS1343_IRQF0);
res = regmap_write(priv->map, DS1343_CONTROL_REG, control);
if (res)
return res;
res = regmap_write(priv->map, DS1343_STATUS_REG, stat);
if (res)
return res;
buf[0] = priv->alarm_sec < 0 || (priv->irqen & RTC_UF) ?
0x80 : bin2bcd(priv->alarm_sec) & 0x7F;
buf[1] = priv->alarm_min < 0 || (priv->irqen & RTC_UF) ?
0x80 : bin2bcd(priv->alarm_min) & 0x7F;
buf[2] = priv->alarm_hour < 0 || (priv->irqen & RTC_UF) ?
0x80 : bin2bcd(priv->alarm_hour) & 0x3F;
buf[3] = priv->alarm_mday < 0 || (priv->irqen & RTC_UF) ?
0x80 : bin2bcd(priv->alarm_mday) & 0x7F;
res = regmap_bulk_write(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
if (res)
return res;
if (priv->irqen) {
control |= DS1343_A0IE;
res = regmap_write(priv->map, DS1343_CONTROL_REG, control);
}
return res;
}
/**
* twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
* @mod_no: module number
* @value: an array of num_bytes+1 containing data to write
* @reg: register address (just offset will do)
* @num_bytes: number of bytes to transfer
*
* Returns the result of operation - 0 is success
*/
int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
{
struct regmap *regmap = twl_get_regmap(mod_no);
int ret;
if (!regmap)
return -EPERM;
ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
value, num_bytes);
if (ret)
pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
DRIVER_NAME, mod_no, reg, num_bytes);
return ret;
}
/**
* st_lsm6dsx_shub_write_reg - write i2c controller register
*
* Write st_lsm6dsx i2c controller register
*/
static int st_lsm6dsx_shub_write_reg(struct st_lsm6dsx_hw *hw, u8 addr,
u8 *data, int len)
{
int err;
mutex_lock(&hw->page_lock);
err = st_lsm6dsx_set_page(hw, true);
if (err < 0)
goto out;
err = regmap_bulk_write(hw->regmap, addr, data, len);
st_lsm6dsx_set_page(hw, false);
out:
mutex_unlock(&hw->page_lock);
return err;
}
/*
* linux rtc-module does not support wday alarm
* and only 24h time mode supported indeed
*/
static int ds3232_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int control, stat;
int ret;
u8 buf[4];
if (ds3232->irq <= 0)
return -EINVAL;
buf[0] = bin2bcd(alarm->time.tm_sec);
buf[1] = bin2bcd(alarm->time.tm_min);
buf[2] = bin2bcd(alarm->time.tm_hour);
buf[3] = bin2bcd(alarm->time.tm_mday);
/* clear alarm interrupt enable bit */
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret)
goto out;
control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
if (ret)
goto out;
/* clear any pending alarm flag */
ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
if (ret)
goto out;
stat &= ~(DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
if (ret)
goto out;
ret = regmap_bulk_write(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
if (ret)
goto out;
if (alarm->enabled) {
control |= DS3232_REG_CR_A1IE;
ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
}
out:
return ret;
}
/* Set current time and date in RTC */
static int rk808_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
struct rk808 *rk808 = rk808_rtc->rk808;
u8 rtc_data[NUM_TIME_REGS];
int ret;
dev_dbg(dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
gregorian_to_rockchip(tm);
rtc_data[0] = bin2bcd(tm->tm_sec);
rtc_data[1] = bin2bcd(tm->tm_min);
rtc_data[2] = bin2bcd(tm->tm_hour);
rtc_data[3] = bin2bcd(tm->tm_mday);
rtc_data[4] = bin2bcd(tm->tm_mon + 1);
rtc_data[5] = bin2bcd(tm->tm_year - 100);
rtc_data[6] = bin2bcd(tm->tm_wday);
/* Stop RTC while updating the RTC registers */
ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
BIT_RTC_CTRL_REG_STOP_RTC_M,
BIT_RTC_CTRL_REG_STOP_RTC_M);
if (ret) {
dev_err(dev, "Failed to update RTC control: %d\n", ret);
return ret;
}
ret = regmap_bulk_write(rk808->regmap, RK808_SECONDS_REG,
rtc_data, NUM_TIME_REGS);
if (ret) {
dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
return ret;
}
/* Start RTC again */
ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
BIT_RTC_CTRL_REG_STOP_RTC_M, 0);
if (ret) {
dev_err(dev, "Failed to update RTC control: %d\n", ret);
return ret;
}
return 0;
}