static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau *adau = snd_soc_component_get_drvdata(component);
if (SND_SOC_DAPM_EVENT_ON(event)) {
adau->pll_regs[5] = 1;
} else {
adau->pll_regs[5] = 0;
/* Bypass the PLL when disabled, otherwise registers will become
* inaccessible. */
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
}
/* The PLL register is 6 bytes long and can only be written at once. */
regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
if (SND_SOC_DAPM_EVENT_ON(event)) {
mdelay(5);
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
}
return 0;
}
static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct s5m_rtc_info *info = dev_get_drvdata(dev);
u8 data[8];
int ret = 0;
switch (info->device_type) {
case S5M8763X:
s5m8763_tm_to_data(tm, data);
break;
case S5M8767X:
ret = s5m8767_tm_to_data(tm, data);
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__,
1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday);
ret = regmap_raw_write(info->rtc, SEC_RTC_SEC, data, 8);
if (ret < 0)
return ret;
ret = s5m8767_rtc_set_time_reg(info);
return ret;
}
static int ___send_obuf(struct mcuio_i2c_dev *i2cd, int space)
{
int togo, l, stat;
togo = i2cd->olen - i2cd->sent;
/*
* Make size an integer multiple of the number of data bytes in
* a single wrb mcuio packet (with fill flag set).
* This is to reduce the mcuio overhead (try sending as few single
* byte packets as possible).
*/
if (space > 8)
space = (space >> 3) << 3;
l = min(space, togo);
pr_debug("%s: space = %d, togo = %d, l = %d, sent = %d\n",
__func__, space, togo, l, i2cd->sent);
stat = regmap_raw_write(i2cd->map_b, I2C_MCUIO_OBUF,
&i2cd->buf[i2cd->sent], l);
if (stat < 0) {
dev_err(&i2cd->mdev->dev, "error sending output buffer\n");
return stat;
}
i2cd->sent += l;
return stat;
}
static int pm805_bulk_write_reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
unsigned int reg = mc->reg;
unsigned char buf[PM805_MIXER_COEFFICIENT_MAX_NUM];
int i, count = 0;
struct pm80x_chip *chip = (struct pm80x_chip *)codec->control_data;
count = (ucontrol->value.integer.value[0] & 0xff);
if (count < 1 || count > PM805_MIXER_COEFFICIENT_MAX_NUM) {
pr_info("error count %d, must between 1~32\n", count);
return -EINVAL;
}
pr_debug("%s: 0x%x, count %d\n", __func__, reg, count);
for (i = 0; i < count; i++) {
buf[i] = (ucontrol->value.integer.value[i + 1]);
pr_debug("value 0x%x\n", buf[i]);
}
return regmap_raw_write(chip->regmap, reg, buf, count);
}
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf)
{
int ret;
ret = regmap_raw_write(da9150->regmap, reg, buf, count);
if (ret)
dev_err(da9150->dev, "Failed to bulk write to reg 0x%x %d\n",
reg, ret);
}
static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = dai->codec;
struct adau *adau = snd_soc_codec_get_drvdata(codec);
unsigned int r, n, m, i, j;
unsigned int div;
int ret;
if (freq_in < 8000000 || freq_in > 27000000)
return -EINVAL;
if (!freq_out) {
r = 0;
n = 0;
m = 0;
div = 0;
} else {
if (freq_out % freq_in != 0) {
div = DIV_ROUND_UP(freq_in, 13500000);
freq_in /= div;
r = freq_out / freq_in;
i = freq_out % freq_in;
j = gcd(i, freq_in);
n = i / j;
m = freq_in / j;
div--;
} else {
r = freq_out / freq_in;
n = 0;
m = 0;
div = 0;
}
if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
return -EINVAL;
}
adau->pll_regs[0] = m >> 8;
adau->pll_regs[1] = m & 0xff;
adau->pll_regs[2] = n >> 8;
adau->pll_regs[3] = n & 0xff;
adau->pll_regs[4] = (r << 3) | (div << 1);
if (m != 0)
adau->pll_regs[4] |= 1; /* Fractional mode */
/* The PLL register is 6 bytes long and can only be written at once. */
ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
if (ret)
return ret;
adau->pll_freq = freq_out;
return 0;
}
int pm860x_bulk_write(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
int ret;
ret = regmap_raw_write(map, reg, buf, count);
return ret;
}
/* Primitive bulk write support for soc-cache. The data pointed to by
* `data' needs to already be in the form the hardware expects. Any
* data written through this function will not go through the cache as
* it only handles writing to volatile or out of bounds registers.
*
* This is currently only supported for devices using the regmap API
* wrappers.
*/
static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec,
unsigned int reg,
const void *data, size_t len)
{
if (!codec->cache_bypass
&& !snd_soc_codec_volatile_register(codec, reg)
&& reg < codec->driver->reg_cache_size)
return -EINVAL;
return regmap_raw_write(codec->control_data, reg, data, len);
}
int sec_rtc_bulk_write(struct sec_pmic_dev *sec_pmic, u32 reg, int count,
u8 *buf)
{
#ifdef CONFIG_EXYNOS_MBOX
int ret;
mutex_lock(&sec_lock);
if (!apm_status)
ret = regmap_raw_write(sec_pmic->rtc_regmap, reg, buf, count);
else {
mutex_lock(&sec_pmic->iolock);
ret = sec_pmic->ops->apm_bulk_write(RTC, reg, buf, count);
mutex_unlock(&sec_pmic->iolock);
if (ret < 0)
ret = regmap_raw_write(sec_pmic->rtc_regmap, reg, buf, count);
}
mutex_unlock(&sec_lock);
return ret;
#else
return regmap_raw_write(sec_pmic->rtc_regmap, reg, buf, count);
#endif
}
static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
{
u8 data[2];
unsigned int tp_read;
int ret;
struct rtc_time tm;
ret = regmap_read(info->rtc, SEC_RTC_UDR_CON, &tp_read);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read control reg(%d)\n",
__func__, ret);
return ret;
}
/* Set RTC control register : Binary mode, 24hour mode */
data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
info->rtc_24hr_mode = 1;
ret = regmap_raw_write(info->rtc, SEC_ALARM0_CONF, data, 2);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
__func__, ret);
return ret;
}
/* In first boot time, Set rtc time to 1/1/2012 00:00:00(SUN) */
if ((tp_read & RTC_TCON_MASK) == 0) {
dev_dbg(info->dev, "rtc init\n");
tm.tm_sec = 0;
tm.tm_min = 0;
tm.tm_hour = 0;
tm.tm_wday = 0;
tm.tm_mday = 1;
tm.tm_mon = 0;
tm.tm_year = 112;
tm.tm_yday = 0;
tm.tm_isdst = 0;
ret = s5m_rtc_set_time(info->dev, &tm);
}
ret = regmap_update_bits(info->rtc, SEC_RTC_UDR_CON,
RTC_TCON_MASK, tp_read | RTC_TCON_MASK);
if (ret < 0)
dev_err(info->dev, "%s: fail to update TCON reg(%d)\n",
__func__, ret);
return ret;
}
static int palmas_rtc_write_block(void *mfd, u8 *data, u8 reg, int no_regs)
{
struct palmas *palmas = mfd;
int slave;
unsigned int addr;
slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
/* twl added extra byte on beginning of block data */
if (no_regs > 1)
data++;
return regmap_raw_write(palmas->regmap[slave], addr, data, no_regs);
}
/* Primitive bulk write support for soc-cache. The data pointed to by
* `data' needs to already be in the form the hardware expects. Any
* data written through this function will not go through the cache as
* it only handles writing to volatile or out of bounds registers.
*
* This is currently only supported for devices using the regmap API
* wrappers.
*/
static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec,
unsigned int reg,
const void *data, size_t len)
{
/* To ensure that we don't get out of sync with the cache, check
* whether the base register is volatile or if we've directly asked
* to bypass the cache. Out of bounds registers are considered
* volatile.
*/
if (!codec->cache_bypass
&& !snd_soc_codec_volatile_register(codec, reg)
&& reg < codec->driver->reg_cache_size)
return -EINVAL;
return regmap_raw_write(codec->control_data, reg, data, len);
}
static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
{
int ret;
u8 data[8];
u8 alarm0_conf;
struct rtc_time tm;
ret = regmap_bulk_read(info->rtc, SEC_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__,
1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday);
switch (info->device_type) {
case S5M8763X:
alarm0_conf = 0x77;
ret = regmap_write(info->rtc, SEC_ALARM0_CONF, alarm0_conf);
break;
case S5M8767X:
data[RTC_SEC] |= ALARM_ENABLE_MASK;
data[RTC_MIN] |= ALARM_ENABLE_MASK;
data[RTC_HOUR] |= ALARM_ENABLE_MASK;
data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
if (data[RTC_DATE] & 0x1f)
data[RTC_DATE] |= ALARM_ENABLE_MASK;
if (data[RTC_MONTH] & 0xf)
data[RTC_MONTH] |= ALARM_ENABLE_MASK;
if (data[RTC_YEAR1] & 0x7f)
data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
ret = regmap_raw_write(info->rtc, SEC_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
ret = s5m8767_rtc_set_alarm_reg(info);
break;
default:
return -EINVAL;
}
return ret;
}
static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct s5m_rtc_info *info = dev_get_drvdata(dev);
u8 data[8];
int ret;
switch (info->device_type) {
case S5M8763X:
s5m8763_tm_to_data(&alrm->time, data);
break;
case S5M8767X:
s5m8767_tm_to_data(&alrm->time, data);
break;
default:
return -EINVAL;
}
dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__,
1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon,
alrm->time.tm_mday, alrm->time.tm_hour, alrm->time.tm_min,
alrm->time.tm_sec, alrm->time.tm_wday);
ret = s5m_rtc_stop_alarm(info);
if (ret < 0)
return ret;
ret = regmap_raw_write(info->rtc, SEC_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
ret = s5m8767_rtc_set_alarm_reg(info);
if (ret < 0)
return ret;
if (alrm->enabled)
ret = s5m_rtc_start_alarm(info);
return ret;
}
static void sc16is7xx_handle_tx(struct uart_port *port)
{
struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
struct circ_buf *xmit = &port->state->xmit;
unsigned int txlen, to_send, i;
if (unlikely(port->x_char)) {
sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
port->icount.tx++;
port->x_char = 0;
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return;
/* Get length of data pending in circular buffer */
to_send = uart_circ_chars_pending(xmit);
if (likely(to_send)) {
/* Limit to size of TX FIFO */
txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
to_send = (to_send > txlen) ? txlen : to_send;
/* Add data to send */
port->icount.tx += to_send;
/* Convert to linear buffer */
for (i = 0; i < to_send; ++i) {
s->buf[i] = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
regcache_cache_bypass(s->regmap, true);
regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
regcache_cache_bypass(s->regmap, false);
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
{
u8 data[8];
int ret, i;
struct rtc_time tm;
ret = regmap_bulk_read(info->rtc, SEC_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__,
1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday);
switch (info->device_type) {
case S5M8763X:
ret = regmap_write(info->rtc, SEC_ALARM0_CONF, 0);
break;
case S5M8767X:
for (i = 0; i < 7; i++)
data[i] &= ~ALARM_ENABLE_MASK;
ret = regmap_raw_write(info->rtc, SEC_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
ret = s5m8767_rtc_set_alarm_reg(info);
break;
default:
return -EINVAL;
}
return ret;
}
/* When loading firmware, host writes firmware data from address 0x8000.
When the address reaches 0x9FFF, the next address should return to 0x8000.
This function handles this address window and load firmware data to AP1302.
win_pos indicates the offset within this window. Firmware loading procedure
may call this function several times. win_pos records the current position
that has been written to.*/
static int ap1302_write_fw_window(struct v4l2_subdev *sd,
u16 *win_pos, const u8 *buf, u32 len)
{
struct ap1302_device *dev = to_ap1302_device(sd);
int ret;
u32 pos;
u32 sub_len;
for (pos = 0; pos < len; pos += sub_len) {
if (len - pos < AP1302_FW_WINDOW_SIZE - *win_pos)
sub_len = len - pos;
else
sub_len = AP1302_FW_WINDOW_SIZE - *win_pos;
ret = regmap_raw_write(dev->regmap16,
*win_pos + AP1302_FW_WINDOW_OFFSET,
buf + pos, sub_len);
if (ret)
return ret;
*win_pos += sub_len;
if (*win_pos >= AP1302_FW_WINDOW_SIZE)
*win_pos = 0;
}
return 0;
}
static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
if (freq_in < 8000000 || freq_in > 27000000)
return -EINVAL;
ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
if (ret < 0)
return ret;
/* The PLL register is 6 bytes long and can only be written at once. */
ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
if (ret)
return ret;
adau->pll_freq = freq_out;
return 0;
}
static int sigma_action_write_regmap(void *control_data,
const struct sigma_action *sa, size_t len)
{
return regmap_raw_write(control_data, be16_to_cpu(sa->addr),
sa->payload, len - 2);
}
int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf)
{
return regmap_raw_write(s5m87xx->regmap, reg, buf, count);
}
static int wm8994_write(struct wm8994 *wm8994, unsigned short reg,
int bytes, const void *src)
{
return regmap_raw_write(wm8994->regmap, reg, src, bytes);
}
int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf)
{
return regmap_raw_write(sec_pmic->regmap, reg, buf, count);
}
static int rt1711h_write8(struct rt1711h_chip *chip, unsigned int reg, u8 val)
{
return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u8));
}
/**
* wm8994_bulk_write: Write multiple WM8994 registers
*
* @wm8994: Device to write to
* @reg: First register
* @count: Number of registers
* @buf: Buffer to write from. Data must be big-endian formatted.
*/
int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg,
int count, const u16 *buf)
{
return regmap_raw_write(wm8994->regmap, reg, buf, count * sizeof(u16));
}
int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
int nr_regs, u8 *data)
{
return regmap_raw_write(pcf->regmap, reg, data, nr_regs);
}
