static inline u32 ccdc_merge(u32 mask, u32 val, u32 offset) { u32 new_val = (regr(offset) & ~mask) | (val & mask); regw(new_val, offset); return new_val; }
static void ccdc_enable(int en) { unsigned int temp; temp = regr(SYNCEN); temp &= (~CCDC_SYNCEN_VDHDEN_MASK); temp |= (en & CCDC_SYNCEN_VDHDEN_MASK); regw(temp, SYNCEN); }
static void ccdc_enable_output_to_sdram(int en) { unsigned int temp; temp = regr(SYNCEN); temp &= (~(CCDC_SYNCEN_WEN_MASK)); temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK); regw(temp, SYNCEN); }
static void* _dp8390read(Dp8390* ctlr, void* to, ulong from, ulong len) { uchar cr; int timo; /* * Read some data at offset 'from' in the card's memory * using the DP8390 remote DMA facility, and place it at * 'to' in main memory, via the I/O data port. */ cr = regr(ctlr, Cr) & ~Txp; regw(ctlr, Cr, Page0|RdABORT|Sta); regw(ctlr, Isr, Rdc); /* * Set up the remote DMA address and count. */ len = ROUNDUP(len, ctlr->width); regw(ctlr, Rbcr0, len & 0xFF); regw(ctlr, Rbcr1, (len>>8) & 0xFF); regw(ctlr, Rsar0, from & 0xFF); regw(ctlr, Rsar1, (from>>8) & 0xFF); /* * Start the remote DMA read and suck the data * out of the I/O port. */ regw(ctlr, Cr, Page0|RdREAD|Sta); rdread(ctlr, to, len); /* * Wait for the remote DMA to complete. The timeout * is necessary because this routine may be called on * a non-existent chip during initialisation and, due * to the miracles of the bus, it's possible to get this * far and still be talking to a slot full of nothing. */ for(timo = 10000; (regr(ctlr, Isr) & Rdc) == 0 && timo; timo--) ; regw(ctlr, Isr, Rdc); regw(ctlr, Cr, cr); return to; }
static void ccdc_enable_output_to_sdram(int en) { unsigned int temp; temp = regr(SYNCEN); temp &= (~(0x1 << 1)); temp |= (en & 0x01) << 1; regw(temp, SYNCEN); }
static void ccdc_enable(int en) { unsigned int temp; temp = regr(SYNCEN); temp &= (~0x1); temp |= (en & 0x01); regw(temp, SYNCEN); }
/* Function to enable/ disable AEW Engine */ inline void aew_engine_setup(int value) { unsigned int pcr; dev_dbg(aewdev, __FUNCTION__ "E\n"); dev_dbg(aewdev, "\nAEW_REG(PCR) Before Setting %x", regr(AEWPCR)); /* Read Pcr Register */ pcr = regr(AEWPCR); pcr &= ~AEW_EN; pcr |= (value << AEW_EN_SHIFT); /*Set AF_EN bit in PCR Register */ regw(pcr, AEWPCR); dev_dbg(aewdev, "\nAfter Setting %d : PCR VALUE %x", value, regr(AEWPCR)); dev_dbg(aewdev, __FUNCTION__ "L\n"); }
/* config_vpif_params * Function to set the parameters of a channel * Mainly modifies the channel ciontrol register * It sets frame format, yc mux mode */ static void config_vpif_params(struct vpif_params *vpifparams, u8 channel_id, u8 found) { const struct vpif_channel_config_params *config = &vpifparams->std_info; u32 value, ch_nip, reg; u8 start, end; int i; start = channel_id; end = channel_id + found; for (i = start; i < end; i++) { reg = vpifregs[i].ch_ctrl; if (channel_id < 2) ch_nip = VPIF_CAPTURE_CH_NIP; else ch_nip = VPIF_DISPLAY_CH_NIP; vpif_wr_bit(reg, ch_nip, config->frm_fmt); vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode); vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT, vpifparams->video_params.storage_mode); /* Set raster scanning SDR Format */ vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT); vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format); if (channel_id > 1) /* Set the Pixel enable bit */ vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT); else if (config->capture_format) { /* Set the polarity of various pins */ vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT, vpifparams->iface.fid_pol); vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT, vpifparams->iface.vd_pol); vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT, vpifparams->iface.hd_pol); value = regr(reg); /* Set data width */ value &= ((~(unsigned int)(0x3)) << VPIF_CH_DATA_WIDTH_BIT); value |= ((vpifparams->params.data_sz) << VPIF_CH_DATA_WIDTH_BIT); regw(value, reg); } /* Write the pitch in the driver */ regw((vpifparams->video_params.hpitch), vpifregs[i].line_offset); } }
void dp8390getea(Ether* ether, uchar* ea) { Dp8390 *ctlr; uchar cr; int i; ctlr = ether->ctlr; /* * Get the ethernet address from the chip. * Take care to restore the command register * afterwards. */ ilock(ctlr); cr = regr(ctlr, Cr) & ~Txp; regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr)); for(i = 0; i < Eaddrlen; i++) ea[i] = regr(ctlr, Par0+i); regw(ctlr, Cr, cr); iunlock(ctlr); }
void dp8390setea(Ether* ether) { int i; uchar cr; Dp8390 *ctlr; ctlr = ether->ctlr; /* * Set the ethernet address into the chip. * Take care to restore the command register * afterwards. Don't care about multicast * addresses as multicast is never enabled * (currently). */ ilock(ctlr); cr = regr(ctlr, Cr) & ~Txp; regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr)); for(i = 0; i < Eaddrlen; i++) regw(ctlr, Par0+i, ether->ea[i]); regw(ctlr, Cr, cr); iunlock(ctlr); }
void ccdc_readregs(void) { unsigned int val = 0; val = regr(ALAW); dev_dbg(vpfe_dev, "\nReading 0x%x to ALAW...\n", val); val = regr(CLAMP); dev_dbg(vpfe_dev, "\nReading 0x%x to CLAMP...\n", val); val = regr(DCSUB); dev_dbg(vpfe_dev, "\nReading 0x%x to DCSUB...\n", val); val = regr(BLKCMP); dev_dbg(vpfe_dev, "\nReading 0x%x to BLKCMP...\n", val); val = regr(FPC_ADDR); dev_dbg(vpfe_dev, "\nReading 0x%x to FPC_ADDR...\n", val); val = regr(FPC); dev_dbg(vpfe_dev, "\nReading 0x%x to FPC...\n", val); val = regr(FMTCFG); dev_dbg(vpfe_dev, "\nReading 0x%x to FMTCFG...\n", val); val = regr(COLPTN); dev_dbg(vpfe_dev, "\nReading 0x%x to COLPTN...\n", val); val = regr(FMT_HORZ); dev_dbg(vpfe_dev, "\nReading 0x%x to FMT_HORZ...\n", val); val = regr(FMT_VERT); dev_dbg(vpfe_dev, "\nReading 0x%x to FMT_VERT...\n", val); val = regr(HSIZE_OFF); dev_dbg(vpfe_dev, "\nReading 0x%x to HSIZE_OFF...\n", val); val = regr(SDOFST); dev_dbg(vpfe_dev, "\nReading 0x%x to SDOFST...\n", val); val = regr(VP_OUT); dev_dbg(vpfe_dev, "\nReading 0x%x to VP_OUT...\n", val); val = regr(SYN_MODE); dev_dbg(vpfe_dev, "\nReading 0x%x to SYN_MODE...\n", val); val = regr(HORZ_INFO); dev_dbg(vpfe_dev, "\nReading 0x%x to HORZ_INFO...\n", val); val = regr(VERT_START); dev_dbg(vpfe_dev, "\nReading 0x%x to VERT_START...\n", val); val = regr(VERT_LINES); dev_dbg(vpfe_dev, "\nReading 0x%x to VERT_LINES...\n", val); }
int vpif_channel_getfid(u8 channel_id) { return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK) >> VPIF_CH_FID_SHIFT; }
static void* dp8390write(Dp8390* ctlr, ulong to, void* from, ulong len) { ulong crda; uchar cr; int timo, width; top: /* * Write some data to offset 'to' in the card's memory * using the DP8390 remote DMA facility, reading it at * 'from' in main memory, via the I/O data port. */ cr = regr(ctlr, Cr) & ~Txp; regw(ctlr, Cr, Page0|RdABORT|Sta); regw(ctlr, Isr, Rdc); len = ROUNDUP(len, ctlr->width); /* * Set up the remote DMA address and count. * This is straight from the DP8390[12D] datasheet, * hence the initial set up for read. * Assumption here that the A7000 EtherV card will * never need a dummyrr. */ if(ctlr->dummyrr && (ctlr->width == 1 || ctlr->width == 2)){ if(ctlr->width == 2) width = 1; else width = 0; crda = to-1-width; regw(ctlr, Rbcr0, (len+1+width) & 0xFF); regw(ctlr, Rbcr1, ((len+1+width)>>8) & 0xFF); regw(ctlr, Rsar0, crda & 0xFF); regw(ctlr, Rsar1, (crda>>8) & 0xFF); regw(ctlr, Cr, Page0|RdREAD|Sta); for(timo=0;; timo++){ if(timo > 10000){ print("ether8390: dummyrr timeout; assuming nodummyrr\n"); ctlr->dummyrr = 0; goto top; } crda = regr(ctlr, Crda0); crda |= regr(ctlr, Crda1)<<8; if(crda == to){ /* * Start the remote DMA write and make sure * the registers are correct. */ regw(ctlr, Cr, Page0|RdWRITE|Sta); crda = regr(ctlr, Crda0); crda |= regr(ctlr, Crda1)<<8; if(crda != to) panic("crda write %lud to %lud", crda, to); break; } } } else{
/* * vdce_hardware_setup :Function to set GE hardware configuration registers */ void vdce_hw_setup(vdce_hw_config_t * register_config) { /* all devdbg will be removed after UT */ int status; dev_dbg(vdce_device, " vdce_hw_setup E\n"); /* setting the hardware register GE ctrl */ regw(register_config->vdce_ctrl, VDCE_CTRL); dev_dbg(vdce_device, "GE CTRL : %x regr = %x \n", register_config->vdce_ctrl, regr(VDCE_CTRL)); regw(register_config->vdce_emulation_ctrl, VDCE_EMULATION_CTRL); dev_dbg(vdce_device, "VDCE_EMULATION_CTRL %x regr = %x\n", register_config->vdce_emulation_ctrl, regr(VDCE_EMULATION_CTRL)); /* setting the hardware register sdr_fmt */ regw(register_config->vdce_sdr_fmt, VDCE_SDR_FMT); dev_dbg(vdce_device, "VDCE_SDR_FMT %x regr = %x\n", register_config->vdce_sdr_fmt, regr(VDCE_SDR_FMT)); /* setting the hardware register req_sz */ regw(register_config->vdce_req_sz, VDCE_REQ_SZ); dev_dbg(vdce_device, "VDCE_REQ_SZ %x regr = %x\n", register_config->vdce_req_sz, regr(VDCE_REQ_SZ)); regw(register_config->vdce_prcs_unit_size, VDCE_PRCS_UNIT_SIZE); dev_dbg(vdce_device, "VDCE_PRCS_UNIT_SIZE : %x regr = %x \n", register_config->vdce_prcs_unit_size, regr(VDCE_PRCS_UNIT_SIZE)); regw(register_config->src_Y_strt_ps, SRC_Y_STRT_PS); dev_dbg(vdce_device, "SRC_Y_STRT_PS : %x regr = %x \n", register_config->src_Y_strt_ps, regr(SRC_Y_STRT_PS)); regw(register_config->src_Y_sz, SRC_Y_SZ); dev_dbg(vdce_device, "SRC_Y_SZ : %x regr = %x \n", register_config->src_Y_sz, regr(SRC_Y_SZ)); regw(register_config->src_C_strt_ps, SRC_C_STRT_PS); dev_dbg(vdce_device, "SRC_C_STRT_PS : %x regr = %x \n", register_config->src_C_strt_ps, regr(SRC_C_STRT_PS)); regw(register_config->src_C_sz, SRC_C_SZ); dev_dbg(vdce_device, "SRC_C_SZ : %x regr = %x \n", register_config->src_C_sz, regr(SRC_C_SZ)); regw(register_config->src_bmp_strt_ps, SRC_BMP_STRT_PS); dev_dbg(vdce_device, "SRC_BMP_STRT_PS : %x regr = %x \n", register_config->src_bmp_strt_ps, regr(SRC_BMP_STRT_PS)); regw(register_config->src_bmp_sz, SRC_BMP_SZ); dev_dbg(vdce_device, "SRC_BMP_SZ : %x regr = %x \n", register_config->src_bmp_sz, regr(SRC_BMP_SZ)); regw(register_config->res_Y_strt_ps, RES_Y_STRT_PS); dev_dbg(vdce_device, "RES_Y_STRT_PS : %x regr = %x \n", register_config->res_Y_strt_ps, regr(RES_Y_STRT_PS)); regw(register_config->res_Y_sz, RES_Y_SZ); dev_dbg(vdce_device, "RES_Y_SZ : %x regr = %x \n", register_config->res_Y_sz, regr(RES_Y_SZ)); regw(register_config->res_C_strt_ps, RES_C_STRT_PS); dev_dbg(vdce_device, "RES_C_STRT_PS : %x regr = %x \n", register_config->res_C_strt_ps, regr(RES_C_STRT_PS)); regw(register_config->res_C_sz, RES_C_SZ); dev_dbg(vdce_device, "RES_C_SZ : %x regr = %x \n", register_config->res_C_sz, regr(RES_C_SZ)); regw(register_config->res_bmp_strt_ps, RES_BMP_STRT_PS); dev_dbg(vdce_device, "RES_BMP_STRT_PS : %x regr = %x \n", register_config->res_bmp_strt_ps, regr(RES_BMP_STRT_PS)); regw(register_config->rsz_mode, RSZ_MODE); dev_dbg(vdce_device, "RSZ_MODE : %x regr = %x \n", register_config->rsz_mode, regr(RSZ_MODE)); regw(register_config->rsz_h_mag, RSZ_H_MAG); dev_dbg(vdce_device, "RSZ_H_MAG : %x regr = %x \n", register_config->rsz_h_mag, regr(RSZ_H_MAG)); regw(register_config->rsz_v_mag, RSZ_V_MAG); dev_dbg(vdce_device, "RSZ_V_MAG : %x regr = %x \n", register_config->rsz_v_mag, regr(RSZ_V_MAG)); regw(register_config->rsz_h_phase, RSZ_H_PHASE); dev_dbg(vdce_device, "RSZ_H_PHASE : %x regr = %x \n", register_config->rsz_h_phase, regr(RSZ_H_PHASE)); regw(register_config->rsz_v_phase, RSZ_V_PHASE); dev_dbg(vdce_device, "RSZ_V_PHASE : %x regr = %x \n", register_config->rsz_v_phase, regr(RSZ_V_PHASE)); regw(register_config->rsz_alf_intensity, RSZ_ALF_INTENSITY); dev_dbg(vdce_device, "RSZ_ALF_INTENSITY : %x regr = %x \n", register_config->rsz_alf_intensity, regr(RSZ_ALF_INTENSITY)); regw(register_config->ccv_mode, CCV_MODE); dev_dbg(vdce_device, "CCV_MODE : %x regr = %x \n", register_config->ccv_mode, regr(CCV_MODE)); regw(register_config->bld_lut[0], BLD_LUT_00); dev_dbg(vdce_device, "BLD_LUT_00 : %x regr = %x \n", register_config->bld_lut[0], regr(BLD_LUT_00)); regw(register_config->bld_lut[1], BLD_LUT_01); dev_dbg(vdce_device, "BLD_LUT_01 : %x regr = %x \n", register_config->bld_lut[1], regr(BLD_LUT_01)); regw(register_config->bld_lut[2], BLD_LUT_02); dev_dbg(vdce_device, "BLD_LUT_02 : %x regr = %x \n", register_config->bld_lut[2], regr(BLD_LUT_02)); regw(register_config->bld_lut[3], BLD_LUT_03); dev_dbg(vdce_device, "BLD_LUT_03 : %x regr = %x \n", register_config->bld_lut[3], regr(BLD_LUT_03)); regw(register_config->rgmp_ctrl, RGMP_CTRL); dev_dbg(vdce_device, "RGMP_CTRL : %x regr = %x \n", register_config->rgmp_ctrl, regr(RGMP_CTRL)); regw(register_config->epd_luma_width, EPD_LUMA_WIDTH); dev_dbg(vdce_device, "EPD_LUMA_WIDTH : %x regr = %x \n", register_config->epd_luma_width, regr(EPD_LUMA_WIDTH)); regw(register_config->epd_chroma_width, EPD_CHROMA_WIDTH); dev_dbg(vdce_device, "EPD_CHROMA_WIDTH : %x regr = %x \n", register_config->epd_chroma_width, regr(EPD_CHROMA_WIDTH)); /* source addres for luma and chroma */ regw(register_config->vdce_src_strt_add_ytop, VDCE_SRC_STRT_ADD_YTOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_YTOP %x regr = %x\n", register_config->vdce_src_strt_add_ytop, regr(VDCE_SRC_STRT_ADD_YTOP)); regw(register_config->vdce_src_strt_add_ctop, VDCE_SRC_STRT_ADD_CTOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_CTOP %x regr = %x\n", register_config->vdce_src_strt_add_ctop, regr(VDCE_SRC_STRT_ADD_CTOP)); regw(register_config->vdce_src_strt_add_ybot, VDCE_SRC_STRT_ADD_YBOT); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_YBOT %x regr = %x\n", register_config->vdce_src_strt_add_ybot, regr(VDCE_SRC_STRT_ADD_YBOT)); regw(register_config->vdce_src_strt_add_cbot, VDCE_SRC_STRT_ADD_CBOT); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_CBOT %x regr = %x\n", register_config->vdce_src_strt_add_cbot, regr(VDCE_SRC_STRT_ADD_CBOT)); /* result address for luma and chroma */ regw(register_config->vdce_res_strt_add_ytop, VDCE_RES_STRT_ADD_YTOP); dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_YTOP %x regr = %x\n", register_config->vdce_res_strt_add_ytop, regr(VDCE_RES_STRT_ADD_YTOP)); regw(register_config->vdce_res_strt_add_ctop, VDCE_RES_STRT_ADD_CTOP); dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_CTOP %x regr = %x\n", register_config->vdce_res_strt_add_ctop, regr(VDCE_RES_STRT_ADD_CTOP)); regw(register_config->vdce_res_strt_add_ybot, VDCE_RES_STRT_ADD_YBOT); dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_YTOP %x regr = %x\n", register_config->vdce_res_strt_add_ybot, regr(VDCE_RES_STRT_ADD_YBOT)); regw(register_config->vdce_res_strt_add_cbot, VDCE_RES_STRT_ADD_CBOT); dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_CBOT %x regr = %x\n", register_config->vdce_res_strt_add_cbot, regr(VDCE_RES_STRT_ADD_CBOT)); /* source offset for luma and chroma */ regw(register_config->vdce_src_add_ofst_ytop, VDCE_SRC_STRT_OFF_YTOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_YTOP %x regr = %x\n", register_config->vdce_src_add_ofst_ytop, regr(VDCE_SRC_STRT_OFF_YTOP)); regw(register_config->vdce_src_add_ofst_ctop, VDCE_SRC_STRT_OFF_CTOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_CTOP %x regr = %x\n", register_config->vdce_src_add_ofst_ctop, regr(VDCE_SRC_STRT_OFF_CTOP)); regw(register_config->vdce_src_add_ofst_ybot, VDCE_SRC_STRT_OFF_YBOT); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_YBOT %x regr = %x\n", register_config->vdce_src_add_ofst_ybot, regr(VDCE_SRC_STRT_OFF_YBOT)); regw(register_config->vdce_src_add_ofst_cbot, VDCE_SRC_STRT_OFF_CBOT); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_CBOT %x regr = %x\n", register_config->vdce_src_add_ofst_cbot, regr(VDCE_SRC_STRT_OFF_CBOT)); /* result offset for luma and chroma */ regw(register_config->vdce_res_strt_off_ytop, VDCE_RES_STRT_OFF_YTOP); dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_YTOP %x regr = %x\n", register_config->vdce_res_strt_off_ytop, regr(VDCE_RES_STRT_OFF_YTOP)); regw(register_config->vdce_res_strt_off_ctop, VDCE_RES_STRT_OFF_CTOP); dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_CTOP %x regr = %x\n", register_config->vdce_res_strt_off_ctop, regr(VDCE_RES_STRT_OFF_CTOP)); regw(register_config->vdce_res_strt_off_ybot, VDCE_RES_STRT_OFF_YBOT); dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_YBOT %x regr = %x\n", register_config->vdce_res_strt_off_ybot, regr(VDCE_RES_STRT_OFF_YBOT)); regw(register_config->vdce_res_strt_off_cbot, VDCE_RES_STRT_OFF_CBOT); dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_CBOT %x regr = %x\n", register_config->vdce_res_strt_off_cbot, regr(VDCE_RES_STRT_OFF_CBOT)); /* bitmap address and offset for luma and chroma */ regw(register_config->vdce_src_strt_add_bmp_top, VDCE_SRC_STRT_ADD_BMP_TOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_BMP_TOP %x regr = %x\n", register_config->vdce_src_strt_add_bmp_top, regr(VDCE_SRC_STRT_ADD_BMP_TOP)); regw(register_config->vdce_src_strt_add_bmp_bot, VDCE_SRC_STRT_ADD_BMP_BOT); dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_BMP_BOT %x regr = %x\n", register_config->vdce_src_strt_add_bmp_bot, regr(VDCE_SRC_STRT_ADD_BMP_BOT)); regw(register_config->vdce_src_strt_off_bmp_top, VDCE_SRC_STRT_OFF_BMP_TOP); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_BMP_TOP %x regr = %x\n", register_config->vdce_src_strt_off_bmp_top, regr(VDCE_SRC_STRT_OFF_BMP_TOP)); regw(register_config->vdce_src_strt_off_bmp_bot, VDCE_SRC_STRT_OFF_BMP_BOT); status = regr(VDCE_STATUS); dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_BMP_BOT %x regr = %x\n", register_config->vdce_src_strt_off_bmp_bot, regr(VDCE_SRC_STRT_OFF_BMP_BOT)); dev_dbg(vdce_device, "vdce_hw_setup L\n"); }
/* Function to set hardware configuration registers */ int aew_register_setup(struct aew_device *aew_dev) { unsigned int pcr = 0, win1 = 0, winstart = 0, blkwin = 0, subwin = 0; dev_dbg(aewdev, __FUNCTION__ "E\n"); /* Set up the registers */ pcr = regr(AEWPCR); /* Enable A Law */ if (aew_dev->config->alaw_enable == H3A_AEW_ENABLE) pcr |= AEW_ALAW_EN; else pcr &= ~AEW_ALAW_EN; /*Configure Saturation limit */ pcr &= ~AVE2LMT; pcr |= aew_dev->config->saturation_limit << AEW_AVE2LMT_SHIFT; /* Set Input Source */ pcr &= ~AEW_INP_SRC; pcr |= (AEW_CCDC) << AEW_INP_SRC_SHIFT; regw(pcr, AEWPCR); /*Window parameter configuration */ /* Configure Window Width in AEWWIN1 register */ win1 = 0; win1 |= ((AEW_SET_VAL(aew_dev->config->window_config.height)) << AEW_WINH_SHIFT); /* Configure Window height in AEWWIN1 register */ win1 |= ((AEW_SET_VAL(aew_dev->config->window_config.width)) << AEW_WINW_SHIFT); /* Configure Window vertical count in AEWWIN2 register */ win1 |= ((aew_dev->config->window_config).vt_cnt - 1) << AEW_VT_COUNT_SHIFT; /* Configure Window horizontal count in AEWWIN1 register */ win1 |= ((aew_dev->config->window_config).hz_cnt - 1); /* Configure Window vertical start in AEWWIN1 register */ regw(win1, AEWWIN1); /*Window Start parameter configuration */ winstart &= ~WINSV; winstart |= (aew_dev->config->window_config).vt_start << AEW_VT_START_SHIFT; /* Configure Window horizontal start in AEWWIN2 register */ winstart &= ~WINSH; winstart |= (aew_dev->config->window_config).hz_start; regw(winstart, AEWINSTART); /*Window Line Increment configuration */ /*Configure vertical line increment in AEWSUBWIN */ subwin &= ~AEWINCV; subwin |= (AEW_SET_VAL(aew_dev->config->window_config. vt_line_incr) << AEW_LINE_INCR_SHIFT); /* Configuring Horizontal Line increment in AEWSUBWIN */ subwin &= ~AEWINCH; subwin |= (AEW_SET_VAL(aew_dev->config->window_config.hz_line_incr)); regw(subwin, AEWSUBWIN); /* Black Window Configuration */ /* Configure vertical start and height in AEWWINBLK */ blkwin &= ~BLKWINSV; blkwin |= (aew_dev->config->blackwindow_config). vt_start << AEW_BLKWIN_VT_START_SHIFT; /* Configure height in Black window */ blkwin &= ~BLKWINH; blkwin |= (AEW_SET_VAL(aew_dev->config->blackwindow_config.height)); regw(blkwin, AEWINBLK); /* Set AFBUFST to Current buffer Physical Address */ regw((unsigned int)(virt_to_phys(aew_dev->buff_curr)), AEWBUFST); dev_dbg(aewdev, "\n PCR is %x", regr(AEWPCR)); dev_dbg(aewdev, "\n SUBWIN is %x", regr(AEWSUBWIN)); dev_dbg(aewdev, "\n WINSTART is %x", regr(AEWINSTART)); dev_dbg(aewdev, "\n WINBLK is %x", regr(AEWINBLK)); dev_dbg(aewdev, "\n WIN1 is %x", regr(AEWWIN1)); dev_dbg(aewdev, "\n AEWBUST %x", regr(AEWBUFST)); AEW_SETGAMMAWD; dev_dbg(aewdev, __FUNCTION__ "L\n"); return 0; }