static void __init pxa1908_reg_init(void)
{
apmu_virt_addr = regs_addr_get_va(REGS_ADDR_APMU);
apbc_virt_addr = regs_addr_get_va(REGS_ADDR_APBC);
mpmu_virt_addr = regs_addr_get_va(REGS_ADDR_MPMU);
icu_virt_addr = regs_addr_get_va(REGS_ADDR_ICU);
APMU_CORE_IDLE_CFG[0] = apmu_virt_addr + CORE0_IDLE;
APMU_CORE_IDLE_CFG[1] = apmu_virt_addr + CORE1_IDLE;
APMU_CORE_IDLE_CFG[2] = apmu_virt_addr + CORE2_IDLE;
APMU_CORE_IDLE_CFG[3] = apmu_virt_addr + CORE3_IDLE;
APMU_CORE_RSTCTRL[0] = apmu_virt_addr + CORE0_RSTCTRL;
APMU_CORE_RSTCTRL[1] = apmu_virt_addr + CORE1_RSTCTRL;
APMU_CORE_RSTCTRL[2] = apmu_virt_addr + CORE2_RSTCTRL;
APMU_CORE_RSTCTRL[3] = apmu_virt_addr + CORE3_RSTCTRL;
APMU_MP_IDLE_CFG[0] = apmu_virt_addr + MP_CFG0;
APMU_MP_IDLE_CFG[1] = apmu_virt_addr + MP_CFG1;
APMU_MP_IDLE_CFG[2] = apmu_virt_addr + MP_CFG2;
APMU_MP_IDLE_CFG[3] = apmu_virt_addr + MP_CFG3;
ICU_GBL_INT_MSK[0] = icu_virt_addr + CORE0_CA7_GLB_INT_MASK;
ICU_GBL_INT_MSK[1] = icu_virt_addr + CORE1_CA7_GLB_INT_MASK;
ICU_GBL_INT_MSK[2] = icu_virt_addr + CORE2_CA7_GLB_INT_MASK;
ICU_GBL_INT_MSK[3] = icu_virt_addr + CORE3_CA7_GLB_INT_MASK;
}
static void __init mmp_pmum_regdump_init(void)
{
pmum_regdump_ops.base = regs_addr_get_va(REGS_ADDR_MPMU);
pmum_regdump_ops.phy_base = regs_addr_get_pa(REGS_ADDR_MPMU);
pmum_regdump_ops.regions = pmum_dump_region;
pmum_regdump_ops.reg_nums = ARRAY_SIZE(pmum_dump_region);
register_regdump_ops(&pmum_regdump_ops);
}
static void pxa1936_plt_suspend_init(void)
{
u32 awucrm = 0;
void __iomem *mpmu = regs_addr_get_va(REGS_ADDR_MPMU);
awucrm = __raw_readl(mpmu + AWUCRM);
awucrm |= (PMUM_AP_ASYNC_INT | PMUM_AP_FULL_IDLE);
__raw_writel(awucrm, mpmu + AWUCRM);
}
static int __init coresight_external_agent_init(void)
{
void __iomem *ciu_base = regs_addr_get_va(REGS_ADDR_CIU);
/* enable access CTI registers for core */
coresight_enable_external_agent(ciu_base + 0xd0);
coresight_enable_external_agent(ciu_base + 0xe0);
coresight_enable_external_agent(ciu_base + 0xf0);
coresight_enable_external_agent(ciu_base + 0xf8);
return 0;
}
static void mmp_pm_powered_up(void)
{
int mpidr, cpu, cluster;
unsigned long flags;
mpidr = read_cpuid_mpidr();
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
BUG_ON(cluster >= MAX_NR_CLUSTERS || cpu >= MAX_CPUS_PER_CLUSTER);
cpu_dcstat_event(cpu_dcstat_clk, cpu, CPU_IDLE_EXIT, MAX_LPM_INDEX);
#ifdef CONFIG_VOLDC_STAT
vol_dcstat_event(VLSTAT_LPM_EXIT, 0, 0);
vol_ledstatus_event(MAX_LPM_INDEX);
#endif
trace_pxa_cpu_idle(LPM_EXIT(0), cpu, cluster);
local_irq_save(flags);
arch_spin_lock(&mmp_lpm_lock);
if (cluster_is_idle(cluster)) {
if (mmp_wake_saved && mmp_idle->ops->restore_wakeup) {
mmp_wake_saved = 0;
mmp_idle->ops->restore_wakeup();
}
/* If hardware really shutdown MP subsystem */
if (!(readl_relaxed(regs_addr_get_va(REGS_ADDR_GIC_DIST) +
GIC_DIST_CTRL) & 0x1)) {
pr_debug("%s: cpu%u: cluster%u is up!\n", __func__, cpu, cluster);
cpu_cluster_pm_exit();
}
}
if (!mmp_pm_use_count[cluster][cpu])
mmp_pm_use_count[cluster][cpu] = 1;
mmp_enter_lpm[cluster][cpu] = 0;
if (mmp_idle->ops->clr_pmu)
mmp_idle->ops->clr_pmu(cpu);
arch_spin_unlock(&mmp_lpm_lock);
local_irq_restore(flags);
}
static void pxa1936_set_wake(int irq, unsigned int on)
{
uint32_t awucrm = 0;
uint32_t apbc_timer0;
void __iomem *apbc = regs_addr_get_va(REGS_ADDR_APBC);
void __iomem *mpmu = regs_addr_get_va(REGS_ADDR_MPMU);
/* setting wakeup sources */
switch (irq) {
/* wakeup line 2 */
case IRQ_PXA1936_GPIO_AP:
awucrm = PMUM_WAKEUP2;
break;
/* wakeup line 3 */
case IRQ_PXA1936_KEYPAD:
awucrm = PMUM_WAKEUP3 | PMUM_KEYPRESS | PMUM_TRACKBALL |
PMUM_NEWROTARY;
break;
/* wakeup line 4 */
case IRQ_PXA1936_AP0_TIMER1:
apbc_timer0 = __raw_readl(apbc + TIMER0);
__raw_writel(0x1 << 7 | apbc_timer0, apbc + TIMER0);
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_1;
break;
case IRQ_PXA1936_AP0_TIMER2:
apbc_timer0 = __raw_readl(apbc + TIMER0);
__raw_writel(0x1 << 7 | apbc_timer0, apbc + TIMER0);
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_2;
break;
case IRQ_PXA1936_AP0_TIMER3:
apbc_timer0 = __raw_readl(apbc + TIMER0);
__raw_writel(0x1 << 7 | apbc_timer0, apbc + TIMER0);
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_3;
break;
case IRQ_PXA1936_AP1_TIMER1:
awucrm = PMUM_WAKEUP4 | PMUM_AP1_TIMER_1;
break;
case IRQ_PXA1936_AP1_TIMER2:
awucrm = PMUM_WAKEUP4 | PMUM_AP1_TIMER_2;
break;
case IRQ_PXA1936_AP1_TIMER3:
awucrm = PMUM_WAKEUP4 | PMUM_AP1_TIMER_3;
break;
case IRQ_PXA1936_AP2_TIMER1:
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_1;
break;
case IRQ_PXA1936_AP2_TIMER2:
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_2;
break;
case IRQ_PXA1936_AP2_TIMER3:
awucrm = PMUM_WAKEUP4 | PMUM_AP0_2_TIMER_3;
break;
case IRQ_PXA1936_RTC_ALARM:
awucrm = PMUM_WAKEUP4 | PMUM_RTC_ALARM;
break;
/* wakeup line 5 */
case IRQ_PXA1936_USB1:
case IRQ_PXA1936_GPS:
awucrm = PMUM_WAKEUP5;
break;
/* wakeup line 6 */
case IRQ_PXA1936_MMC:
awucrm = PMUM_WAKEUP6 | PMUM_SDH_23 | PMUM_SQU_SDH1;
break;
/* wakeup line 7 */
case IRQ_PXA1936_PMIC:
awucrm = PMUM_WAKEUP7;
break;
default:
/* do nothing */
break;
}
if (on) {
if (awucrm) {
awucrm |= __raw_readl(mpmu + AWUCRM);
__raw_writel(awucrm, mpmu + AWUCRM);
}
} else {
if (awucrm) {
awucrm = ~awucrm & __raw_readl(mpmu + AWUCRM);
__raw_writel(awucrm, mpmu + AWUCRM);
}
}
}
