static noinline void socrates_entry(void)
{
int ret;
arm_early_mmu_cache_invalidate();
relocate_to_current_adr();
setup_c();
socfpga_lowlevel_init(&cm_default_cfg,
sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table));
puts_ll("lowlevel init done\n");
puts_ll("SDRAM setup...\n");
socfpga_sdram_mmr_init();
puts_ll("SDRAM calibration...\n");
ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
ac_rom_init, ac_rom_init_size);
if (ret)
hang();
puts_ll("done\n");
barebox_arm_entry(0x0, SZ_1G, 0);
}
__noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2)
{
relocate_to_current_adr();
setup_c();
tqmls1046a_r_entry(r0);
}
__noreturn void barebox_single_pbl_start(unsigned long membase,
unsigned long memsize, void *boarddata)
{
uint32_t offset;
uint32_t pg_start, pg_end, pg_len;
void __noreturn (*barebox)(unsigned long, unsigned long, void *);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
endmem -= STACK_SIZE; /* stack */
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
relocate_to_current_adr();
/* Get offset between linked address and runtime address */
offset = get_runtime_offset();
pg_start = (uint32_t)&input_data - offset;
pg_end = (uint32_t)&input_data_end - offset;
pg_len = pg_end - pg_start;
if (IS_ENABLED(CONFIG_RELOCATABLE))
barebox_base = arm_barebox_image_place(membase + memsize);
else
barebox_base = TEXT_BASE;
if (offset && (IS_ENABLED(CONFIG_PBL_FORCE_PIGGYDATA_COPY) ||
region_overlap(pg_start, pg_len, barebox_base, pg_len * 4))) {
/*
* copy piggydata binary to its link address
*/
memcpy(&input_data, (void *)pg_start, pg_len);
pg_start = (uint32_t)&input_data;
}
setup_c();
if (IS_ENABLED(CONFIG_MMU_EARLY)) {
endmem &= ~0x3fff;
endmem -= SZ_16K; /* ttb */
mmu_early_enable(membase, memsize, endmem);
}
endmem -= SZ_128K; /* early malloc */
free_mem_ptr = endmem;
free_mem_end_ptr = free_mem_ptr + SZ_128K;
pbl_barebox_uncompress((void*)barebox_base, (void *)pg_start, pg_len);
arm_early_mmu_cache_flush();
flush_icache();
if (IS_ENABLED(CONFIG_THUMB2_BAREBOX))
barebox = (void *)(barebox_base + 1);
else
barebox = (void *)barebox_base;
barebox(membase, memsize, boarddata);
}
static void __imx53_guf_vincell_init(int is_lt)
{
arm_early_mmu_cache_invalidate();
imx5_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
barrier();
imx53_guf_vincell_init(is_lt);
}
ENTRY_FUNCTION(prep_start_barebox_karo_tx28, r0, r1, r2)
{
void (*back)(unsigned long) = (void *)get_lr();
relocate_to_current_adr();
setup_c();
karo_tx28_init();
back(0);
}
static void noinline uncompress(uint32_t membase,
uint32_t memsize, uint32_t boarddata)
{
uint32_t offset;
uint32_t pg_len;
void __noreturn (*barebox)(uint32_t, uint32_t, uint32_t);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
uint32_t *ptr;
void *pg_start;
arm_early_mmu_cache_invalidate();
endmem -= STACK_SIZE; /* stack */
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
relocate_to_current_adr();
/* Get offset between linked address and runtime address */
offset = get_runtime_offset();
if (IS_ENABLED(CONFIG_RELOCATABLE))
barebox_base = arm_barebox_image_place(membase + memsize);
else
barebox_base = TEXT_BASE;
setup_c();
if (IS_ENABLED(CONFIG_MMU_EARLY)) {
endmem &= ~0x3fff;
endmem -= SZ_16K; /* ttb */
mmu_early_enable(membase, memsize, endmem);
}
endmem -= SZ_128K; /* early malloc */
free_mem_ptr = endmem;
free_mem_end_ptr = free_mem_ptr + SZ_128K;
ptr = (void *)__image_end;
pg_start = ptr + 1;
pg_len = *(ptr);
pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
arm_early_mmu_cache_flush();
flush_icache();
if (IS_ENABLED(CONFIG_THUMB2_BAREBOX))
barebox = (void *)(barebox_base + 1);
else
barebox = (void *)barebox_base;
barebox(membase, memsize, boarddata);
}
ENTRY_FUNCTION(prep_start_barebox_freescale_mx28evk, r0, r1, r2)
{
void (*back)(unsigned long) = (void *)get_lr();
relocate_to_current_adr();
setup_c();
freescale_mx28evk_init();
back(0);
}
ENTRY_FUNCTION(start_imx7s_element14_warp7, r0, r1, r2)
{
imx7_cpu_lowlevel_init();
arm_early_mmu_cache_invalidate();
relocate_to_current_adr();
setup_c();
barrier();
warp7_start();
}
ENTRY_FUNCTION(start_imx6_wandboard, r0, r1, r2)
{
imx6_cpu_lowlevel_init();
arm_setup_stack(0x0091ffb0);
relocate_to_current_adr();
setup_c();
barrier();
wandboard_start();
}
ENTRY_FUNCTION(start_am33xx_afi_gf_sram, bootinfo, r1, r2)
{
am33xx_save_bootinfo((void *)bootinfo);
/*
* Setup C environment, the board init code uses global variables.
* Stackpointer has already been initialized by the ROM code.
*/
relocate_to_current_adr();
setup_c();
gf_sram_init();
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2)
{
am33xx_save_bootinfo((void *)bootinfo);
arm_cpu_lowlevel_init();
/*
* Setup C environment, the board init code uses global variables.
* Stackpointer has already been initialized by the ROM code.
*/
relocate_to_current_adr();
setup_c();
pcm051_board_init();
}
ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2)
{
void *fdt;
const unsigned int system_type = get_system_type();
vf610_cpu_lowlevel_init();
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
switch (system_type) {
default:
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
relocate_to_current_adr();
setup_c();
puts_ll("\n*********************************\n");
puts_ll("* Unknown system type: ");
puthex_ll(system_type);
puts_ll("\n* Assuming devboard revision B\n");
puts_ll("*********************************\n");
}
case ZII_PLATFORM_VF610_DEV_REV_B: /* FALLTHROUGH */
fdt = __dtb_vf610_zii_dev_rev_b_start;
break;
case ZII_PLATFORM_VF610_SCU4_AIB:
fdt = __dtb_vf610_zii_scu4_aib_start;
break;
case ZII_PLATFORM_VF610_DEV_REV_C:
fdt = __dtb_vf610_zii_dev_rev_c_start;
break;
case ZII_PLATFORM_VF610_CFU1:
fdt = __dtb_vf610_zii_cfu1_start;
break;
case ZII_PLATFORM_VF610_SSMB_SPU3:
fdt = __dtb_vf610_zii_ssmb_spu3_start;
break;
case ZII_PLATFORM_VF610_SPB4:
fdt = __dtb_vf610_zii_spb4_start;
break;
case ZII_PLATFORM_VF610_SSMB_DTU:
fdt = __dtb_vf610_zii_ssmb_dtu_start;
break;
}
vf610_barebox_entry(fdt + get_runtime_offset());
}
void __noreturn barebox_multi_pbl_start(unsigned long membase,
unsigned long memsize, void *boarddata)
{
uint32_t pg_len;
void __noreturn (*barebox)(unsigned long, unsigned long, void *);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
uint32_t *image_end;
void *pg_start;
unsigned long pc = get_pc();
image_end = (void *)ld_var(__image_end) - get_runtime_offset();
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
/*
* If we run from inside the memory just relocate the binary
* to the current address. Otherwise it may be a readonly location.
* Copy and relocate to the start of the memory in this case.
*/
if (pc > membase && pc - membase < memsize)
relocate_to_current_adr();
else
relocate_to_adr(membase);
}
/*
* image_end is the first location after the executable. It contains
* the size of the appended compressed binary followed by the binary.
*/
pg_start = image_end + 1;
pg_len = *(image_end);
if (IS_ENABLED(CONFIG_RELOCATABLE))
barebox_base = arm_mem_barebox_image(membase, endmem,
pg_len);
else
barebox_base = TEXT_BASE;
setup_c();
pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
if (IS_ENABLED(CONFIG_MMU_EARLY)) {
unsigned long ttb = arm_mem_ttb(membase, endmem);
pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
mmu_early_enable(membase, memsize, ttb);
}
free_mem_ptr = arm_mem_early_malloc(membase, endmem);
free_mem_end_ptr = arm_mem_early_malloc_end(membase, endmem);
pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx\n",
pg_start, pg_len, barebox_base);
pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
arm_early_mmu_cache_flush();
flush_icache();
if (IS_ENABLED(CONFIG_THUMB2_BAREBOX))
barebox = (void *)(barebox_base + 1);
else
barebox = (void *)barebox_base;
pr_debug("jumping to uncompressed image at 0x%p\n", barebox);
barebox(membase, memsize, boarddata);
}
